KD11-E/EA microcode

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The engineering drawings for the KD11-E CPU and KD11-EA CPU provide nice flow charts for the microcode in these CPUs; with one tiny exception, the microcode in the two is identical. (The KD11-EA contains additional microcode associated with the FP11-A Floating-Point Processor, which is not covered here.)

The difference is that the microinstruction 17-JJ is stored in location 002 in the KD11-E, and location 0744 in the KD11-EA. The reason for the change is unknown.

The instructions/functionality covered on each page are as follows:

Page Contents
2 Instruction fetch and dispatch
3 Double op, source fetch
4 MOV
5 Double op, byte or SUB
6 Double op, destination fetch
7 Single op, modified dest
8 Single op, non-modified dest
9 JMP
10 JSR
11 SWAB
12 Shift, rotate
13 MFPI
14 MTPI
15 MTPS
16 MFPS
17 MARK, BR, RTS, CLx, SEx, SOB, RTI, RTT, NEG, WAIT, RESET
18 MUL/DIV
19 MUL
20 MUL
21 DIV
22 DIV
23 ASH/ASHC
24 Shift right
25 Shift left
26 Power on, trap

The following table, indexed by microinstruction number (in octal), gives the location of each microinstruction in the flow diagrams, the next microinstruction(s), and the operation performed by that microinstruction.

The microengine of the KD11-E/EA uses a technique called a 'branch microtest' (abbreviated to 'BUT' in the drawings), where the 'next microinstruction' field (in each microinstruction - there is no 'micro-PC') can be OR'd with various bits, to provide conditional branching. More than one bit at a time can be OR'd, thereby providing multi-way branching.

One microinstruction (015), the main dispatch in instruction decoding, greatly extends the technique (with the aid of an instruction decode ROM), so the next microinstruction in its case may be one of dozens. They are arranged in groups of eight, one for each addressing mode in the operands. (In the table below, such a destination is notated as 'YYx'.)

During the transcription of this information, a number of errors in the drawings were found - places were two different microinstructions were assigned to the same location. These have been corrected (and checked against a dump of the microcode).

μinstruction μcode flow diagram location operation
000 2-A Service intr/trap, store vector
001 26-M Move PC to B
002
003 17-LL Initialize system for 150msec
004 17-L Destination register to PC
005 13-E Fetch destination address, enable previous mode
006 17-R PSW to R12
007 17-X PSW to R12
 
010 14-D Fetch word from top of stack
011 17-EE Fetch top of stack
012 17-NN No operation
013 17-OO Vector to R15
014 17-MM Service interrupt/trab, fetch vector
015 2-C Increment PC, ubranch on instruction
016 2-B Fetch next instruction, load into IR
017 26-A Move vector to R15
 
020 17-A Sign extend BREG
021 9-A Jump address to PC
022 9-C Jump address to BREG
023 9-D Fetch jump address
024 9-B Decrement RDST, enable stack overflow
025 9-G Decrement RDST, enable stack overflow
026 9-I Fetch index data
027 9-L Fetch index data
 
030 11-A Swap destination operatand to R12
031 11-C Fetch swapped destination operand
032 11-E Fetch swapped destination operand
033 11-G Fetch destination address
034 11-D Decrement RDST, enable stack overflow
035 11-I Decrement RDST, enable stack overflow
036 11-K Fetch index data
037 11-N Fetch index data
 
040 7-A Operate and load condition codes
041 7-B Fetch destination operand
042 7-D Fetch destination operand
043 7-F Fetch destination address
044 7-C Decrement RDST, enable stack overflow
045 7-H Decrement RDST, enable stack overflow
046 7-K Fetch index data
047 7-M Fetch index data
 
050 4-A Operate and load condition codes
051 4-B Set up destination address
052 4-P Set up destination address, increment RDST
053 4-F Fetch destination address
054 4-C Decrement RDST, enable stack overflow
055 4-H Decrement RDST, enable stack overflow
056 4-J Fetch index data
057 4-M Fetch index data
 
060 6-A Destination operand to BREG
061 6-B Fetch destination operand
062 6-D Fetch destination operand
063 6-F Fetch destination address
064 6-C Decrement RDST, enable stack overflow
065 6-I Decrement RDST, enable stack overflow
066 6-L Fetch index data
067 6-O Fetch index data
 
070 5-A Destination operand to BREG
071 5-B Fetch destination operand
072 5-D Fetch destination operand
073 5-F Fetch destination address
074 5-C Decrement RDST, enable stack overflow
075 5-H Decrement RDST, enable stack overflow
076 5-K Fetch index data
077 5-N Fetch index data
 
 
100 13-A Destination data to R12, enable previous mode
101 13-B Move destination address to R12
102 13-D Move destination address to R12
103 13-G Fetch destination address
104 13-C Decrement RDST, enable stack overflow
105 13-I Decrement RDST, enable stack overflow
106 13-K Fetch index data
107 13-N Fetch index data
 
110 3-A Source operand to R12 and BREG
111 3-B Fetch source operand
112 3-D Fetch source operand
113 3-F Fetch source address
114 3-C Decrement RSRC, enable stack overflow
115 3-H Decrement RSRC, enable stack overflow
116 3-K Fetch index data
117 3-N Fetch index data
 
120 15-A Destination operand to R12 and BREG
121 15-F Fetch destination operand
122 15-H Fetch destination operand
123 15-J Fetch destination address
124 15-G Decrement RDST, enable stack overflow
125 15-M Decrement RDST, enable stack overflow
126 15-O Fetch index data
127 15-R Fetch index data
 
130 16-A PSW data to R12
131 16-C Place destination address on bus address lines
132 16-F Destination address to bus, increment RDST
133 16-G Fetch destination address
134 16-E Decrement RDST, enable stack overflow
135 16-J Decrement RDST, enable stack overflow
136 16-L Fetch index data
137 16-O Fetch index data
 
140 17-U RDST to BREG
141 4-G Increment RDST
142 4-I Fetch destination address
143 4-Q Setup destination address, enable KT maintenance
144 4-K Increment PC
145 4-L Determine destination address
146 4-N Increment PC
147 4-O Determine address of destination address
 
150 17-KK Zero R12
151 10-A Jump address to BREG
152 10-C Jump address to BREG
153 10-D Fetch jump address
154 10-B Decrement RDST, jump address to BREG
155 10-F Decrement RDST, enable stack overflow
156 10-H Fetch index data
157 10-K Fetch index data
 
160 8-A Operate on operand, load condition codesx
161 8-B Fetch destination operand
162 8-D Fetch destination operand
163 8-F Fetch destination address
164 8-C Decrement RDST, enable stack overflow
165 8-H Decrement RDST, enable stack overflow
166 8-K Fetch index data
167 8-N Fetch index data
 
170 12-A Destination operand to BREG
171 12-C Fetch destination operand
172 12-E Fetch destination operand
173 12-G Fetch destination addressa
174 12-D Decrement RDST, enable stack overflow
175 12-I Decrement RDST, enable stack overflow
176 12-L Fetch index data
177 12-O Fetch index data
 
 
200 17-I Sign extend BREG
201 26-FF Set R15 to 26
202 26-GG Fetch new PSW
203 17-Q Operate, set condition codes
204 17-W Operate, set condition codes
205 3-E Increment RSRC
206 3-G Increment RSRC
207 3-I Fetch source address
 
210 17-T Operate, send condition codes
211 3-J Fetch source operand
212 3-L Increment PC
213 3-M Determine source address
214 3-O Increment PC
215 3-P Determine address of source address
216 3-Q Fetch source address
217 4-E Get destination data and store, enable KT maintenance
 
220 18-A Fetch multiplicand/divisor
221 18-B Fetch multiplicand/divisor
222 18-D Fetch multiplicand/divisor
223 18-F Fetch destination address
224 18-C Decrement RDST, enable stack overflow
225 18-H Decrement RDST, enable stack overflow
226 18-J Fetch index data
227 18-M Fetch index data
 
230 23-A Fetch shift count
231 23-B Fetch shift count
232 23-D Fetch shift count
233 23-F Fetch destination address
234 23-C Decrement RDST, enable stack overflow
235 23-H Decrement RDST, enable stack overflow
236 23-J Fetch index data
237 23-M Fetch index data
 
240 17-V RSRC to BREG
241 4-P Fetch destination address
242 5-E Increment RDST
243 5-G Increment RDST
244 5-I Fetch destination address
245 5-J Fetch destination operand
246 5-L Increment PC
247 5-M Determine destination address
 
250 14-A Move data to desination register
251 14-B Move destination address to R13
252 14-F Move destination address to R13
253 14-H Fetch destination address
254 14-C Decrement RDST, enable stack overflow
255 14-I Decrement RDST, enable stack overflow
256 14-K Fetch index data
257 14-N Fetch index data
 
260 17-Z Decrement RSRC, branch on 0
261 5-P Determine address of destination address
262 5-Q Fetch destination address
263 6-E Increment RDST
264 6-G Increment RDST
265 6-H Operate and load condition codes
266 6-J Fetch destination address
267 6-K Fetch destination operand
 
270 17-P RDEST to BREG
271 6-N Determine destination address
272 6-P Increment PC
273 6-Q Determine address of destination address
274 6-R Fetch destination address
275 7-E Increment RDST
276 7-G Increment RDST
277 7-I Fetch destination address
 
 
300 7-J Fetch destination operand
301 7-L Increment PC
302 7-M Determine destination address
303 7-O Increment PC
304 7-P Determine address of destination address
305 7-Q Fetch destination address
306 8-E Increment RDST
307 8-G Increment RDST
 
310 8-I Fetch destination address
311 8-J Fetch destination operand
312 8-L Increment PC
313 8-M Determine desination address
314 8-O Increment PC
315 8-P Determine address of desination address
316 8-Q Fetch destination address
317 9-E Increment RDST
 
320 9-F Jump address to PC
321 9-H Fetch jump address
322 9-J Increment PC
323 9-K Determine jump address
324 9-M Increment PC
325 9-N Determine address of jump address
326 9-O Fetch jump address
327 10-E Increment RDST
 
330 10-G Fetch jump address
331 10-I Increment PC
332 10-J Determine jump address
333 10-L Increment PC
334 10-M Determine address of jump address
335 10-N Fetch jump address
336 10-O Decrement SP
337 10-P Set up bus address
 
3401 10-Q Output RSRC to stack
341 10-R Move PC to RSRC
342 10-S BREG to PC
343 11-B Load condition codes
344 11-F Increment RDST
345 11-H Increment RDST
346 11-J Fetch destination address
347 11-L Increment PC
 
350 11-M Determine destination address
351 11-O Increment PC
352 11-P Determine address of destination address
353 11-Q Fetch destination address
354 11-R Fetch swapped destination address
355 11-S Store data, load condition codes
356 12-B Shift operand
3572 12-F Increment RDST
 
360 12-H Increment RDST
361 12-J Fetch destination address
362 12-K Fetch destination operand
363 12-M Increment PC
364 12-N Determine destination address
365 12-P Increment PC
366 12-Q Determine address of destination address
367 12-R Fetch destination address
 
370 12-S Shift operand
371 13-F Increment RDST
372 13-H Increment RDST
373 13-J Fetch destination address
374 13-L Increment PC
375 13-M Determine destination address
376 13-O Increment PC
377 13-P Determine address of destination address
 
 
400 18-S Complement & test sign of multiplicand
401 18-T Test divisor for zero
402 19-A Zero R17 and B, test multiplicand
403 19-J Put multiplier in BX
404 21-A Put one's complement of divisor in R13
405 19-D Put one's complement of multiplier in R13
406 22-W Set V bit
407 19-U Shift right (partial product, multiplier), decrement counter
 
410 20-C Test upper product for all 1's
411 20-L Clear C bit
412 20-H Test lower product for zero
413 19-M Shift right (partial product, multiplier), decrement counter
414 20-J Test MSB of lower product
415 20-G Set C bit
416 20-I Set Z bit
417 19-P Store upper product
 
420 20-E Set V bit
421 21-L Fetch lower dividend
422 20-D Test MSB of lower product
423 21-F Take one's complement of upper dividend
424 21-M Shift upper dividend left, test sign of divisor
425 21-O Subtract divisor from dividend, test remainder
426 22-S Set V bit
427 19-L Subtract multiplicand from partial product
 
430 25-A Test counter for 0, fetch upper part of operand
431 22-J Clear V bit
432 26-N Move PC to R5
433 19-T Add multiplicand to partial product
434 24-A Test IR9 to determine ASH/ASHC
435 21-N Subtract divisor from dividend, test remainder
436 17-D BREG to SP
437 19-Q Store upper product
 
440 21-P Test first quotient bit
441 22-B Add divisor to remainder
442 21-G Shift remainder left, test sign of divisor, test LSB of quotient
443 22-N Srore remainder
444 22-D Srore remainder
445 24-E Save BX in B, clear N bit
446 22-A Test quotient LSB and sign of divisor
447 24-D Save BX in B, clear N bit
 
4503 17-II Step SP
451 22-K Add divisor to remainder
452 25-D Test IR9 to determine ASH/ASHC, fetch lower part of operand
453 19-O Subtract multiplicand from partial product
454 24-K Clear C bit
455 13-R Fetch destination data, enable previous mode
456 25-B Test IR9 to determine ASH/ASHC
457 19-R Store upper product
 
460 26-B Move PSW to B
461 22-C Test sign of dividend
462 22-Y Set V bit
463 13-S Decrement SP
464 24-U Store lower result, clear N bit
465 24-X Clear Z bit
466 24-T Store lower result, clear N bit, test for 0
467 24-W Clear Z bit
 
470 26-C Increment vector address
471 22-L Test sign of dividend
472 13-P Set up bus address
473 19-N Shift right (partial product, multiplier), decrement counter
474 14-G Increment RDST
475 14-J Fetch destination address
476 14-L Increment PC
477 19-S Store upper product
 
 
500 25-C Clear BX to indicate C bit = 0
501 25-M No operation
502 19-I Zero R17 and B
503 19-B Put multiplier in R12 and test sign
504 26-D Fetch new PSW
505 19-C Put one's complement of multiplier in R13
506 14-D Increment PC
507 19-F Shift right (100000, 100000)
 
510 14-P Determine address of destination address
511 20-K Set C bit
512 24-C Store upper result, test sign of Z bit
513 14-R Setup bus address, enable previous mode
514 14-Q Fetch destination address
515 20-F Clear C bit
516 24-B Shift upper part of operand
517 24-O Fetch lower part of operand
 
520 14-S Output data to destination address
521 21-C Fetch lower dividend
522 17-J Shift BREG left one bit
523 17-K Add offset to PC
524 22-V Set V bit
525 17-M Fetch top of stack
526 22-R Clear V bit
527 17-N Step stack to pointer
 
530 22-G Clear U bit
531 22-I Set V bit
532 22-H Clear N bit, set Z bit
533 17-O Load stack data into destination register
534 22-Q Clear V bit
535 17-GG Step SP
536 22-P Clear N bit, set Z bit
537 17-HH Fetch top of stack
 
540 26-KK Clear IR to halt processor
541 17-S Mask and set condition codes
542 17-Y Mask and set condition codes
543 22-M Srore remainder
544 22-E Srore remainder
545 24-F Save BX in B, set N bit
546 17-CC Calculate offset
547 17-DD Subtract offset from PC
 
550 24-M Clear C bit
551 17-G Data to R5
552 14-M Determine destination address
553 17-B Shift BREG left, R5 to BXREG
554 24-L Set C bit
555 17-C Add PC to BREG
556 17-E BXREG to PC
557 17-F Fetch top of stack
 
560 26-E R6 <- R6-2, enable stack overflow
561 17-H Step SP
562 26-F Place SP address on bus lines
563 18-E Increment RDST
564 24-V Store lower result, set N bit
565 18-G Increment RDST
566 26-G Output old PSW, enable double bus errors
567 18-I Fetch destination address
 
570 26-H Decrement SP, enable stack overflow
571 18-K Increment PC
572 26-I Place SP address on bus lines
573 26-J Push old PC on stack
574 18-L Determine destination address
575 18-N Increment PC
576 18-O Determine address of destination address
577 26-K Decrement vector address
 
 
600 18-P Fetch destination address
601 18-Q Fetch multiplicand/divisor
602 18-R Load step counter, test IR9 for multiply/divide
603 19-E Test two's complement of multiplier
604 19-G Load B and R5 with 040000
605 19-H Zero lower product
606 19-K Test LSB of BX for first multiply step
607 20-A Store lower product
 
610 20-B C out is the sign of the product
611 20-M Transfer condition codes to PSW
612 21-B Fetch upper dividend and test sign
613 21-D Take two's complement of lower dividend
614 22-F Store quotient, clear N bit
615 22-O Store quotient, set N bit
616 22-T Clear C bit
617 22-U Transfer condition codes to PSW
 
620 22-X Set C bit
621 23-E Increment RDST
622 23-G Increment RDST
623 21-E Take two's complement of upper dividend
624 23-I Fetch destination address
625 23-K Increment PC
626 23-L Determine destination address
627 23-N Increment PC
 
630 23-O Determine address of destination address
631 23-P Fetch destination address
632 23-Q Fetch shift count
633 23-R Test sign of counter
634 24-G Set Z bit
635 24-H Clear Z bit
636 24-I V bit <- OVX
637 24-J V bit <- OVX
 
640 21-J Add divisor to remainder, test counter sign
641 24-N Transfer condition codes to PSW
642 14-E Increment SP
643 13-Q Fetch destination address
644 14-T Move stack data to R12
645 17-FF Data to PC
646 26-L Fetch new PC
647 26-CC Add 2 to R15
 
650 21-K Add divisor to remainder, test counter sign
651 25-N Store upper result, test sign of Z bit
652 25-H Clear BX so that 0's shift into B
653 25-E Shift double operand left, decrement counter
654 26-DD Set R15 to 5
655 25-K Clear BX to indicate C bit is 0
656 26-EE Set R15 to 013
657 25-F Test R17 to determine C bit
 
660 21-H Subtract divisor from remainder, test counter sign
661 5-O Increment PC
662 6-M Increment PC
663 15-I Increment RDST
664 15-K Increment RDST
665 15-N Fetch destination address
666 15-L Fetch destination operand
667 15-P Increment PC
 
670 21-I Subtract divisor from remainder, test counter sign
671 15-Q Determine destination address
672 15-S Increment PC
673 15-T Determine address of destination address
674 15-U Fetch destination address
675 15-B Set R17 to all 1's
676 15-C Set R17 equal to PSW address
677 15-D Place PSW address on bus address lines
 
 
700 17-BB Swap bytes, shift BREG left
701 20-N Test upper product for zero
702 17-AA No operation
703 24-R Clear counter to indicate C bit is 0
704 15-E Output destination operand to PSW
705 16-B Move R12 to RDST
706 16-D Move PSW data to R12
707 24-Q Shift double operand right, increment counter
 
710 16-H Increment RDST
711 16-K Fetch destination address
712 16-M Increment PC
713 16-N Determine destination address
714 16-P Increment PC
715 16-Q Determine address of destination address
716 16-R Fetch destination address
717 16-I Place destination address on bus address lines
 
720 26-HH Clear IR to halt processor
721 26-Z Shift B left, zero B LSB
722 26-Q Put all 1's in the PC
723 24-S Store upper result, test sign of Z bit
724 26-S Move all 1's to B
725 26-AA Increment PC, branch on COUT
726 26-II Clear IR to halt processor
727 24-P Shift double operand right, increment counter
 
730 26-JJ Clear IR to halt processor
731 26-O Clear PC
732 26-U Move 016 to counter
733 26-P Test for 0 PC
734 26-R Test for 0 PC
735 26-T XOR PC and B
736 26-V Clear B
737 26-X Move B to BX
 
740 26-BB Clear R15
741 26-LL No operation
742 26-Y Add PC and BX, decrement count
743 26-W Put 1 in B
744 17-JJ Data to PSW
745
746
747
 
750
751 25-G Set counter to indicate C bit is 1
752
753 25-I Shift single operand left, decrement counter
754
755 25-L Set BX to indicate C bit is 1
756
757 25-J Test R17 to determine C bit
 
760
761
762
763
764
765
766
767
 
770
771
772
773
774
775
776
777

Notes:

1 - prints say 346; '6' written for '0'
2 - prints say 375; digit swap
3 - prints say 540; digit swap

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