Difference between revisions of "KD11-E CPU"

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==KY11-LB Interface==
 
==KY11-LB Interface==
  
The interface to the KY11-LB is carried over two 10-wire cables connected to Berg headers (denominated J1 and J2) on the M7266 module; these carried the [[micro-PC]] (from the CPU), and 'Manual Clock Enable' and 'Manual Clock' lines. The pinout is:
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The interface to the KY11-LB is carried over two 10-wire cables connected to Berg headers (denominated J1 and J2) on the M7266 module.
 
 
J1:
 
 
 
# Micro-PC 04
 
# Micro-PC 01
 
# Micro-PC 02
 
# Micro-PC 03
 
# Manual Clock Enable
 
# Micro-PC 00
 
# Micro-PC 05
 
# Micro-PC 06
 
# Micro-PC 07
 
# Manual Clock
 
 
 
J2:
 
 
 
# Micro-PC 08
 
  
 
{{PDP-11}}
 
{{PDP-11}}

Revision as of 16:34, 1 July 2017

The KD11-E CPU was the first CPU version for the PDP-11/34; it consisted of two hex boards, the M7265 Data Paths module and the M7266 Control module.

Although it supported the KY11-LB Programmer's Console, including the maintainence functionality which allow the CPU's microcode to be single-stepped, it did not support the FP11-A floating point unit or the KK11-A cache; a PDP-11/34 system needed the upgraded KD11-EA CPU for that.

KY11-LB Interface

The interface to the KY11-LB is carried over two 10-wire cables connected to Berg headers (denominated J1 and J2) on the M7266 module.