Difference between revisions of "KD11-Z CPU"

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The KD11-Z used the [[Extended UNIBUS]] for its [[bus]] to [[main memory]], allowing it to have up to 4 mega-[[byte]]s of main memory. All devices were attached to a semi-separate [[UNIBUS]] (it and the EUB shared data lines, but not address lines); [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and mapped UNIBUS addresses to main memory addresses.
 
The KD11-Z used the [[Extended UNIBUS]] for its [[bus]] to [[main memory]], allowing it to have up to 4 mega-[[byte]]s of main memory. All devices were attached to a semi-separate [[UNIBUS]] (it and the EUB shared data lines, but not address lines); [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and mapped UNIBUS addresses to main memory addresses.
  
Full [[PDP-11 Memory Management]] and a [[cache]] (the [[KK11-C Cache Memory|KK11-B]]) were standard on all KD11-Z's. It also supported the optional [[FP11-F Floating-Point Processor|FP11-F]] [[floating point]] (full [[FP11 floating point]]) and/or the [[KE44-A Commercial Instruction Set Processor]] (it could work with either, or both); these plugged into dedicated slots in the CPU [[backplane]].
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Full [[PDP-11 Memory Management]] and a [[cache]] (the [[KK11-C Cache Memory|KK11-B]]) were standard on all KD11-Z's. It also supported the optional [[FP11-F Floating-Point Processor|FP11-F]] [[floating point]] (full [[FP11 floating point]]) and/or the [[KE44-A Commercial Instruction Set Processor]]; these plugged into dedicated slots in the CPU [[backplane]] (it could work with either, or both).
  
 
==Details==
 
==Details==

Revision as of 16:18, 11 May 2018

The KD11-Z CPU was the CPU of the PDP-11/44; the letter code 'Z' was a tip to the fact that it was the last native UNIBUS PDP-11 CPU, and the last to be made out of discrete chips, and not a microprocessor.

The KD11-Z used the Extended UNIBUS for its bus to main memory, allowing it to have up to 4 mega-bytes of main memory. All devices were attached to a semi-separate UNIBUS (it and the EUB shared data lines, but not address lines); DMA devices could gain access to the memory via a UNIBUS map which connected the two, and mapped UNIBUS addresses to main memory addresses.

Full PDP-11 Memory Management and a cache (the KK11-B) were standard on all KD11-Z's. It also supported the optional FP11-F floating point (full FP11 floating point) and/or the KE44-A Commercial Instruction Set Processor; these plugged into dedicated slots in the CPU backplane (it could work with either, or both).

Details

The basic KD11-Z it consisted of five hex boards:

  • M7094 Data Path module
  • M7095 Control module
  • M7096 Multifunction module
  • M7097 KK11-B Cache module
  • M7098 UNIBUS interface module

In addition, a single dual board, the M7090 Console Interface module, held a number of Berg connector headers used for various input/output functions.