KDF11-U CPU pinout

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The KDF11-U CPU of the PDP-11/24 plugs into a specially-wired slot of the -11/24 backplane. Some of the customization relates to the semi-separate UNIBUS, and Extended UNIBUS used between the CPU and main memory; others are part of the connection between the CPU and the optional UNIBUS map board, the KT24.

The table below provides the complete, detailed pinout (as far as the Field Maintenance Print Set shows) of the edge connector of the CPU PCB. Pins are identified in the usual DEC manner: pin 'XYz' is on connector 'X'; contact land 'Y' of that connector; and 'z' identifies the side. The 'Location' gives the location of the connection in the KDF11-U engineering drawings: 'Kx' is the page number, and the second field, of the form 'Xn', are the coordinates on that page. Pins which appear on multiple pages have multiple locations.

Pins with blank 'Location' fields mostly do not seem to be connected to anything; 'Signals' listed for such pins are those usually seen on those pins in MUD and SPC slots (which is what the transcribed list started with); they not be of any value in reality.

Pin Location Signal
AA1 K9-B1 BMIB00
AA2 K3-B7 +5V
AB1 K9-B1 BMIB01
AB2   Boot Enable
AC1 K9-B1 BMIB02
AC2 K3-B6 Gnd
AD1 K9-B1 BMIB03
AD2 K13-B6 DAL16 H
AE1 K9-B1 BMIB04
AE2 K12-C2 BSIO H
AF1 K9-B1 BMIB05
AF2   D05
AH1 K9-A1 BMIB06
AH2 K13-A5 MREPLY L
AJ1 K9-A1 BMIB07
AJ2 K13-A5 ABORT L
AK1 K9-D1 BMIB08
AK2 K9-D1 BMIB11
AL1 K9-D1 BMIB09
AL2 K9-C1 BMIB12
AM1 K9-D1 BMIB10
AM2 K9-C1 BMIB13
AN1 K11-C4 MA21
AN2 K9-C1 BMIB14
AP1 K11-B4 MA20
AP2   BBSY
AR1 K6-A3 BOOT ENABLE L
AR2 K13-B6 DAL18 H
AS1  
AS2 K13-B6 DAL17 H
AT1 K3-A6 Gnd
AT2 K9-C1 BMIB15
AU1 K13-A5 UBMAP L
AU2 K1-B6 LREAD L
AV1 K13-B8 +5V
AV2 K13-A6 DMMUS L
BA1 K1-A6 C0 H
BA2 K3-B7 +5V
BB1 K13-B6 DAL19 H
BB2 K1-D5 MCLK L
BC1 K1-A6 LAT ADD 5
BC2 K3-B6 Gnd
BD1 K13-B6 DAL21 H
BD2 K13-B6 DAL20 H
BE1 K11-B4 MA19
BE2 K11-B4 MA18
BF1 K3-A3; K6-A5 BUS ACLO
BF2 K3-A2; K6-A5 BUS DCLO
BH1 K11-B4 MA01
BH2 K11-A4 MA00
BJ1 K11-A6 MA03
BJ2 K11-A6 MA02
BK1 K11-B6 MA05
BK2 K11-B6 MA04
BL1 K11-B6 MA07
BL2 K11-B6 MA06
BM1 K11-C6 MA09
BM2 K11-C6 MA08
BN1 K11-D6 MA11
BN2 K11-C6 MA10
BP1 K11-D6 MA13
BP2 K11-D6 MA12
BR1 K11-C4 MA15
BR2 K11-C4 MA14
BS1 K11-D4 MA17
BS2 K11-D4 MA16
BT1 K3-A6 Gnd
BT2 K11-A4 MC1
BU1 K1-B6 BUS REQ L
BU2 K11-A4 MC0
BV1 K1-B1 MEM MSYN L
BV2 K1-C6 DIN H
CA1  
CA2 K3-B7 +5V
CB1 K3-D6; K10-A3 BUS NPG
CB2  
CC1 K2-D8; K3-C5 BUS PA
CC2 K3-B6 Gnd
CD1 K6-D8 LINE CLOCK
CD2 K3-D6; K5-C3 BUS D15
CE1 K1-D6 CT0 H
CE2 K3-C5; K5-C3 BUS D14
CF1 K1-D6 CT1 H
CF2 K3-D8; K5-C3 BUS D13
CH1 K3-D8; K5-B3 BUS D11
CH2 K3-C5; K5-C3 BUS D12
CJ1 K1-D1 ENB A&C H
CJ2 K3-C5; K5-B3 BUS D10
CK1 K1-A8 E39p26 D9
CK2 K3-D8; K5-B3 BUS D09
CL1 K2-C2 INT BOOT SSYN L
CL2 K3-C7; K5-B3 BUS D08
CM1 K4-B7 DIR IN L
CM2 K3-D8; K4-C3 BUS D07
CN1 K11-D4 I/O PAGE H
CN2 K3-C7; K4-C3 BUS D04
CP1 K6-A6 HALT REQ L
CP2 K3-D8; K4-C3 BUS D05
CR1 K1-A1 HALT GRANT L
CR2 K3-D8; K4-B3 BUS D01
CS1 K2-D8; K3-D6 BUS PB
CS2 K3-C7; K4-A3 BUS D00
CT1 K3-A6 Gnd
CT2 K3-D8; K4-B3 BUS D03
CU1 K12-D5 +15V
CU2 K3-C7; K4-B3 BUS D02
CV1   AC LO
CV2 K3-C7; K4-C3 BUS D06
DA1 K7-D1 CHIP RESET H
DA2 K3-B7 +5V
DB1 K7-C3 COMB CSEL L
DB2  
DC1 K4-A5 BDAL00
DC2 K3-B6 Gnd
DD1 K4-A5 BDAL01
DD2 K3-C5; K6-B6 BUS BR7
DE1 K4-A5 BDAL02
DE2 K3-D6; K6-B6 BUS BR6
DF1 K4-A5 BDAL03
DF2 K3-C3; K6-C6 BUS BR5
DH1 K4-D5 BDAL04
DH2 K3-C3; K6-C6 BUS BR4
DJ1 K4-D5 BDAL05
DJ2 K5-D6 BDAL15
DK1 K4-D5 BDAL06
DK2 K5-D6 BDAL14
DL1 K2-D3; K3-C7 BUS INIT
DL2 K3-D6; K10-D6 BUS BG7
DM1 K4-D5 BDAL07
DM2  
DN1 K5-A5 BDAL08
DN2 K3-D6; K10-D6 BUS BG6
DP1 K5-A5 BDAL09
DP2  
DR1 K5-A5 BDAL10
DR2 K3-D4; K10-D6 BUS BG5
DS1 K5-A5 BDAL11
DS2  
DT1 K3-A6 Gnd
DT2 K3-D4; K10-C6 BUS BG4
DU1 K5-D6 BDAL13
DU2 K2-C6 MMU CYC L
DV1  
DV2 K5-C6 BDAL12
EA1  
EA2 K3-B7 +5V
EB1  
EB2  
EC1 K3-D2; K11-D7 BUS A12
EC2 K3-B6 Gnd
ED1 K3-C1; K11-D5 BUS A17
ED2 K3-C1; K11-D5 BUS A15
EE1 K2-D3; K3-C1 BUS MSYN
EE2 K3-D2; K11-D5 BUS A16
EF1 K3-D4; K11-A7 BUS A02
EF2 K3-D2; K11-A5 BUS C1
EH1 K3-C3; K11-A5 BUS A01
EH2 K3-D4; K11-A5 BUS A00
EJ1 K2-D3; K3-C1 BUS SSYN
EJ2 K3-D2; K11-A5 BUS C0
EK1 K3-D2; K11-D5 BUS A14
EK2 K3-C1; K11-D7 BUS A13
EL1 K3-C1; K11-D7 BUS A11
EL2 K12-D6 SO2
EM1  
EM2 K12-D6 SO1
EN1  
EN2 K3-D2; K11-C7 BUS A08
EP1 K3-D2; K11-D7 BUS A10
EP2 K3-C3; K11-C7 BUS A07
ER1 K3-C1; K11-C7 BUS A09
ER2 K1-C1 BUS MSTR L
ES1 K7-C7 UPPER 128K H
ES2 K1-A5 QV HOLD L
ET1 K3-A6 Gnd
ET2 K7-C7 LBSIO H
EU1 K3-D4; K11-C7 BUS A06
EU2 K3-D4; K11-A7 BUS A04
EV1 K3-C3; K11-A7 BUS A05
EV2 K3-C3; K11-A7 BUS A03
FA1  
FA2 K3-B7 +5V
FB1  
FB2 K12-C6 -15V
FC1   SSYN
FC2 K3-B6 Gnd
FD1 K2-D3; K3-C5 BUS BBSY
FD2 K12-A8 +5VF
FE1 K11-B6 UB TO MA VIA UBMAP L
FE2   D02
FF1   D05
FF2 K9-B5 E93p12
FH1   D07
FH2  
FJ1 K3-D6; K10-B8 BUS NPR
FJ2 K9-C3 E106p7
FK1   D08
FK2 K12-D8 SI2 H
FL1 K1-B2 ALLOW MEM MSYN H
FL2 K12-D8 SI2 L
FM1 K3-C7 BUS INTR
FM2 K12-C8 SI1 L
FN1 K12-D4 DATA TERM RDY 2
FN2 K12-C8 SI1 H
FP1 K12-D4 DATA TERM RDY 1
FP2 K12-A5 DC ON
FR1 K12-D8 REMOTE H
FR2 K12-A5 RUN
FS1 K12-D8 REMOTE L
FS2 K12-B4 FPBOOT
FT1 K3-A6 Gnd
FT2 K3-C5; K6-B6; K10-A1 BUS SACK
FU1 K12-C4 CPU RUN L
FU2 K12-B4 FPHALT
FV1  
FV2 K12-A4 FPENB BREAK

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