Difference between revisions of "KDJ11-A CPU"
m (note not used in the spec 11/73) |
m (Proper cat) |
||
| (3 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
[[Image:KDJ11-A.jpg|150px|thumb|right|KDJ11-A CPU]] | [[Image:KDJ11-A.jpg|150px|thumb|right|KDJ11-A CPU]] | ||
| − | The '''KDJ11-A''' CPU board (M8192) is the first [[QBUS]] [[CPU]] card using the [[J-11]] | + | The '''KDJ11-A''' CPU board (M8192) is the first [[QBUS]] [[CPU]] card using the [[J-11 chip set]] of the [[PDP-11]]. It is a [[DEC card form factor|dual-height]] board, and was used to upgrade [[PDP-11/23]] systems. (Confusingly, no DEC 'PDP-11/xx' system is specified as using the KDJ11-A.) |
It contains an 8K-byte write-through cache (set size 1, block size 1 16-bit word), protected by parity; cache control logic inspects [[DMA]] transfers and invalidates cache entries for memory which is written to by a device. | It contains an 8K-byte write-through cache (set size 1, block size 1 16-bit word), protected by parity; cache control logic inspects [[DMA]] transfers and invalidates cache entries for memory which is written to by a device. | ||
| Line 9: | Line 9: | ||
Although the J-11 does implement FP11 floating-point, the board can use the FPJ11 Floating Point Accelerator (note that only the -YB version of the board operates correctly with the FPJ11). | Although the J-11 does implement FP11 floating-point, the board can use the FPJ11 Floating Point Accelerator (note that only the -YB version of the board operates correctly with the FPJ11). | ||
| − | {{ | + | {{PDP-11}} |
| − | + | [[Category: PDP-11 Processors]] | |
| − | [[Category: | + | [[Category: QBUS Processors]] |
| − | [[Category:QBUS | ||
Revision as of 17:41, 17 February 2018
The KDJ11-A CPU board (M8192) is the first QBUS CPU card using the J-11 chip set of the PDP-11. It is a dual-height board, and was used to upgrade PDP-11/23 systems. (Confusingly, no DEC 'PDP-11/xx' system is specified as using the KDJ11-A.)
It contains an 8K-byte write-through cache (set size 1, block size 1 16-bit word), protected by parity; cache control logic inspects DMA transfers and invalidates cache entries for memory which is written to by a device.
It also provides a set of diagnostic LEDs, and a Line Time Clock; but no other devices (boot PROM, serial line, etc).
Although the J-11 does implement FP11 floating-point, the board can use the FPJ11 Floating Point Accelerator (note that only the -YB version of the board operates correctly with the FPJ11).
| v • d • e PDP-11 Computers and Peripherals |
|---|
| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
