Difference between revisions of "KI10"

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{{Infobox Machine
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| name = KI10
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| manufacturer = [[Digital Equipment Corporation]]
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| architecture = [[PDP-10]]
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| year design started = December, 1969
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| year first shipped = May, 1972
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| form factor = [[mainframe]]
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| word size = 36 bits
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| physical address = 22 bits
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| virtual address = 18 bits
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| logic type = [[TTL]] [[IC]]s
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| design type =  clocked synchronous
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| clock speed = 1 μsec
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| memory speed = 1.0 μsec (fast), 1.8 μsec (slow)
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| memory mgmt = [[paging]], 512-word pages
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| operating system = [[TOPS-10]], [[TENEX]]
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| predecessor = [[KA10]]
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| successor = [[KL10]]
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| price = US$200K (CPU), US$500K-1M (system)
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}}
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The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[TTL]] [[chip]]s, on [[FLIP CHIP]] cards.
 
The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[TTL]] [[chip]]s, on [[FLIP CHIP]] cards.
  
 
It was used in later[[DECsystem-10]] models, running [[TOPS-10]]. It was the first PDP-10 model to provide [[paging]] in its as-shipped form.
 
It was used in later[[DECsystem-10]] models, running [[TOPS-10]]. It was the first PDP-10 model to provide [[paging]] in its as-shipped form.

Revision as of 23:28, 5 August 2017


KI10
Manufacturer: Digital Equipment Corporation
Architecture: PDP-10
Year Design Started: December, 1969
Year First Shipped: May, 1972
Form Factor: mainframe
Word Size: 36 bits
Logic Type: TTL ICs
Design Type: clocked synchronous
Clock Speed: 1 μsec
Memory Speed: 1.0 μsec (fast), 1.8 μsec (slow)
Physical Address Size: 22 bits
Virtual Address Size: 18 bits
Memory Management: paging, 512-word pages
Operating System: TOPS-10, TENEX
Predecessor(s): KA10
Successor(s): KL10
Price: US$200K (CPU), US$500K-1M (system)


The KI10 was the second generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of TTL chips, on FLIP CHIP cards.

It was used in laterDECsystem-10 models, running TOPS-10. It was the first PDP-10 model to provide paging in its as-shipped form.