Difference between revisions of "KI10"

From Computer History Wiki
Jump to: navigation, search
(fmt, models)
(bus details)
Line 23: Line 23:
  
 
The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic|TTL]] [[integrated circuit|chip]]s, on [[FLIP CHIP]] cards.
 
The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic|TTL]] [[integrated circuit|chip]]s, on [[FLIP CHIP]] cards.
 +
 +
It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.
  
 
It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.
 
It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.
  
It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.
+
==Busses==
 +
 
 +
[[Image:KBusQCUnlatched.jpg|250px|thumb|right|Memory bus Quick Latch connector (in unlatched position)]]
 +
 
 +
Although the KI10 [[CPU]] provided two each memory bus and I/O bus connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).
  
 
==External links==
 
==External links==

Revision as of 19:24, 12 October 2021


KI10
Manufacturer: Digital Equipment Corporation
Architecture: PDP-10
Year Design Started: December, 1969
Year First Shipped: May, 1972
Form Factor: mainframe
Word Size: 36 bits
Logic Type: TTL ICs
Design Type: clocked synchronous
Clock Speed: 1 μsec
Memory Speed: 1.0 μsec (fast), 1.8 μsec (slow)
Physical Address Size: 22 bits
Virtual Address Size: 18 bits
Memory Management: paging, 512-word pages
Operating System: TOPS-10, TENEX, TYMCOM-X
Predecessor(s): KA10
Successor(s): KL10
Price: US$200K (CPU), US$500K-1M (system)


KI10 at Tymshare

The KI10 was the second generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of TTL chips, on FLIP CHIP cards.

It was the first PDP-10 model to provide paging in its as-shipped form, with 512-word pages. It was initially released in a single-CPU version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.

It was used in later DECsystem-10 models, running TOPS-10. Via a series of kludges, it was also possible to run TENEX on the as-shipped hardware.

Busses

Memory bus Quick Latch connector (in unlatched position)

Although the KI10 CPU provided two each memory bus and I/O bus connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).

External links