Difference between revisions of "KI10"

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(Picture.)
(Very rarely called "PDP-10I".)
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| physical address = 22 bits
 
| physical address = 22 bits
 
| virtual address = 18 bits
 
| virtual address = 18 bits
| logic type = [[TTL]] [[IC]]s
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| logic type = [[transistor-transistor logic|TTL]] [[IC]]s
 
| design type =  clocked synchronous
 
| design type =  clocked synchronous
 
| clock speed = 1 μsec
 
| clock speed = 1 μsec
 
| memory speed = 1.0 μsec (fast), 1.8 μsec (slow)
 
| memory speed = 1.0 μsec (fast), 1.8 μsec (slow)
 
| memory mgmt = [[paging]], 512-word pages
 
| memory mgmt = [[paging]], 512-word pages
| operating system = [[TOPS-10]], [[TENEX]]
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| operating system = [[TOPS-10]], [[TENEX]], [[TYMCOM-X]]
 
| predecessor = [[KA10]]
 
| predecessor = [[KA10]]
 
| successor = [[KL10]]
 
| successor = [[KL10]]
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}}
 
}}
  
The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[TTL]] [[chip]]s, on [[FLIP CHIP]] cards.
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[[Image:Sys37a.jpg|thumb|300px|left|KI10 at Tymshare]]
  
It was used in later[[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.
+
The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic|TTL]] [[integrated circuit|chip]]s, on [[FLIP CHIP]] cards.
  
It was the first PDP-10 model to provide [[paging]] in its as-shipped form. It was initially released in a single-[[processor]] version; a two-CPU version was released later.
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It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.
  
[[Image:Sys37a.jpg|thumb|left|KI10 at Tymshare]]
+
It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.
  
 +
A few documents refer to the KI10-based system as PDP-10I.
  
[[Category:DEC CPUs]]
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==Busses==
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[[Image:KBusQCUnlatched.jpg|250px|thumb|right|Memory bus Quick Latch connector (in unlatched position)]]
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Although the KI10 [[CPU]] provided two each memory bus and I/O bus connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).
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==External links==
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* [http://www.bitsavers.org/pdf/dec/pdp10/KI10/ BitSavers KI10 documents]
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** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/A_Document_On_The_KI10_Apr73.pdf A Document On The KI10]
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** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/KI10ProcMaintMan.pdf KI10 Central Processor Maintenance Manual]
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* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1]
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* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2]
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[[Category: PDP-10 Processors]]

Revision as of 07:38, 11 January 2022


KI10
Manufacturer: Digital Equipment Corporation
Architecture: PDP-10
Year Design Started: December, 1969
Year First Shipped: May, 1972
Form Factor: mainframe
Word Size: 36 bits
Logic Type: TTL ICs
Design Type: clocked synchronous
Clock Speed: 1 μsec
Memory Speed: 1.0 μsec (fast), 1.8 μsec (slow)
Physical Address Size: 22 bits
Virtual Address Size: 18 bits
Memory Management: paging, 512-word pages
Operating System: TOPS-10, TENEX, TYMCOM-X
Predecessor(s): KA10
Successor(s): KL10
Price: US$200K (CPU), US$500K-1M (system)


KI10 at Tymshare

The KI10 was the second generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of TTL chips, on FLIP CHIP cards.

It was the first PDP-10 model to provide paging in its as-shipped form, with 512-word pages. It was initially released in a single-CPU version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.

It was used in later DECsystem-10 models, running TOPS-10. Via a series of kludges, it was also possible to run TENEX on the as-shipped hardware.

A few documents refer to the KI10-based system as PDP-10I.

Busses

Memory bus Quick Latch connector (in unlatched position)

Although the KI10 CPU provided two each memory bus and I/O bus connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).

External links