Difference between revisions of "MASSBUS"

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The '''MASSBUS''' was a high-speed I/O [[bus]] devised by [[DEC]], and used to connect DEC systems to high-speed disk drives and tape controllers such as the [[RP04]], [[RP06]], [[TM02]] and [[TM03]]. A single MASSBUS can contain up to 8 entities.
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The '''MASSBUS''' was a high-speed I/O [[bus]] devised by [[DEC]], and used to connect DEC systems to high-speed disk drives and tape controllers such as the [[RP04]], [[RP06]], [[TM02]] and [[TM03]].
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The fact that the MASSBUS connects to disk '''drives''' and tape 'controllers''' causes terminological difficulties, since there is also a 'conroller' to connect the MASSBUS to the host computer. Hence, the term 'entity' will be used in this article to refer, generically, to things connected to the MASSBUS> A single MASSBUS can contain up to 8 entities.
  
 
A variety of controllers existed to connect MASSBUS devices to various kinds of DEC systems: the [[RH10]] for the [[PDP-10]], the [[RH20]] for the [[KL10]], the [[RH11]] for the [[UNIBUS]] (usually on a [[PDP-11]]), the [[RH70]] for the [[PDP-11/70]], the [[RH750]] for the VAX-11/75x, and the [[RH780]] for the [[Synchronous Backplane Interconnect]] bus found on VAX-11/78x, VAX 86xx, etc.
 
A variety of controllers existed to connect MASSBUS devices to various kinds of DEC systems: the [[RH10]] for the [[PDP-10]], the [[RH20]] for the [[KL10]], the [[RH11]] for the [[UNIBUS]] (usually on a [[PDP-11]]), the [[RH70]] for the [[PDP-11/70]], the [[RH750]] for the VAX-11/75x, and the [[RH780]] for the [[Synchronous Backplane Interconnect]] bus found on VAX-11/78x, VAX 86xx, etc.
  
The MASSBUS contained two separate sections: an asynchronous control section, and a synchronous data transfer section. The two sections operate completely independently. The control section is used to allow the [[CPU]] access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bit and 16-bit (later 32-bit) architectures.
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==Internal details==
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The MASSBUS contained two separate sections (effectively, separate busses): an asynchronous control section (the 'Control Bus'), and a synchronous data transfer section (the 'Data Bus'). The two sections operate completely independently.
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The control section is used to allow the [[CPU]] access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bit and 16-bit (later 32-bit) architectures.
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===Control Bus lines===
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The Control Bus contains the following signals:
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* Control Lines 0:!5 - used to transfer control data
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* Control Lines Parity
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* Drive Select 0:2 - selects the entity
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* Register Select 0:4
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* Controller to Drive - direction of transfer
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* Demand - set by the controller to initiate a transfer
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* Transfer - acknowledgement from the entity
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* Attention - set by an entity to notify the controller
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* Initialize - set by the controller
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* MASSBUS Fail - set by the controller to indicate power loss

Revision as of 17:38, 7 November 2016

The MASSBUS was a high-speed I/O bus devised by DEC, and used to connect DEC systems to high-speed disk drives and tape controllers such as the RP04, RP06, TM02 and TM03.

The fact that the MASSBUS connects to disk drives and tape 'controllers causes terminological difficulties, since there is also a 'conroller' to connect the MASSBUS to the host computer. Hence, the term 'entity' will be used in this article to refer, generically, to things connected to the MASSBUS> A single MASSBUS can contain up to 8 entities.

A variety of controllers existed to connect MASSBUS devices to various kinds of DEC systems: the RH10 for the PDP-10, the RH20 for the KL10, the RH11 for the UNIBUS (usually on a PDP-11), the RH70 for the PDP-11/70, the RH750 for the VAX-11/75x, and the RH780 for the Synchronous Backplane Interconnect bus found on VAX-11/78x, VAX 86xx, etc.

Internal details

The MASSBUS contained two separate sections (effectively, separate busses): an asynchronous control section (the 'Control Bus'), and a synchronous data transfer section (the 'Data Bus'). The two sections operate completely independently.

The control section is used to allow the CPU access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bit and 16-bit (later 32-bit) architectures.

Control Bus lines

The Control Bus contains the following signals:

  • Control Lines 0:!5 - used to transfer control data
  • Control Lines Parity
  • Drive Select 0:2 - selects the entity
  • Register Select 0:4
  • Controller to Drive - direction of transfer
  • Demand - set by the controller to initiate a transfer
  • Transfer - acknowledgement from the entity
  • Attention - set by an entity to notify the controller
  • Initialize - set by the controller
  • MASSBUS Fail - set by the controller to indicate power loss