Difference between revisions of "MF10 core memory"

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The '''MF10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on easly [[[KL10]]s. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An MF10 contained either 32KW or 64KW, and had a [[cycle time]] of 1.0 µseconds.
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The '''MF10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on early [[KL10]]s. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An MF10 contained either 32KW or 64KW, and had a [[cycle time]] of 1.0 µseconds.
  
 
It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.  
 
It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.  
  
Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19. depending; respectively).
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Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively).
  
 
[[Category: PDP-10 memories]]
 
[[Category: PDP-10 memories]]

Revision as of 20:57, 7 March 2019

The MF10 was a core main memory system for the mid-period PDP-10s, principally the KI10, although it was also used on early KL10s. It connected to the so-called external memory bus of either the 18-bit or 22-bit address form. An MF10 contained either 32KW or 64KW, and had a cycle time of 1.0 µseconds.

It was a multi-port memory, with 4 ports per memory system: each port can be independently disabled. The CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.

Each port could be independently set for its address, and for either 2- or 4-way interleaving (using address bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively).