Difference between revisions of "MS11-P MOS memory"
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| − | The '''MS11-P''' (M8743) is a [[Extended UNIBUS]] [[Dynamic RAM|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]]. | + | The '''MS11-P''' (M8743) is a [[Extended UNIBUS]] [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]]. |
It has [[Error-correcting code|ECC]] which automagically corrects single-[[bit]] errors, <!--(at a slight penalty in [[access time|response time]] when an error occurs)--> and detects double-bit errors. | It has [[Error-correcting code|ECC]] which automagically corrects single-[[bit]] errors, <!--(at a slight penalty in [[access time|response time]] when an error occurs)--> and detects double-bit errors. | ||
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On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly. | On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly. | ||
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| + | It uses +5V only, unlike the earlier [[MS11-L MOS memory|MS11-L]] and [[MS11-M MOS memory|MS11-M]] MOS memories. | ||
[[Category: EUB Memories]] | [[Category: EUB Memories]] | ||
Revision as of 15:47, 22 January 2020
The MS11-P (M8743) is a Extended UNIBUS MOS DRAM main memory card. As an EUB card, it can therefore only be plugged into the EUB slots on the PDP-11/24 or PDP-11/44 backplane.
It has ECC which automagically corrects single-bit errors, and detects double-bit errors.
It is a hex-height card, and holds 1 Mbyte when fully populated with 64Kx1 DRAM chips. The memory is arranged as 8 banks, each 16 data bits wide, with 6 additional bits for the ECC.
On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For diagnostic purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.
It uses +5V only, unlike the earlier MS11-L and MS11-M MOS memories.
