Difference between revisions of "PDP-11/45"

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{{Infobox Machine
 
{{Infobox Machine
 
| name=PDP-11/45
 
| name=PDP-11/45
| manufacturer=[[Digital Equipment Corporation]]  
+
| manufacturer=[[Digital Equipment Corporation|DEC]]
 +
| architecture=[[PDP-11 architecture|PDP-11]]
 +
| form factor=[[minicomputer]]
 
| word size= 16 bit
 
| word size= 16 bit
 
| virtual address= 16 bit
 
| virtual address= 16 bit
 
| physical address= 18 bit
 
| physical address= 18 bit
 +
| design type=[[microcode]]d
 
| bus arch= [[UNIBUS]]/FastBus
 
| bus arch= [[UNIBUS]]/FastBus
 
| year introduced= June 1972
 
| year introduced= June 1972
|
 
 
|}}
 
|}}
  
The '''PDP-11/45''' was a fast [[UNIBUS]] [[PDP-11]] system using the KB11-A (early units, prior to 1976) or KB11-D (later) CPU, a high-performance CPU implemented in [[SSI]] [[Schottky TTL]] logic. (The difference between the two was whether they worked with the [[FP11-B]] or [[FP11-C]] [[Floating point processor|FPP]].)
+
The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units), high-performance [[Central Processing Unit|CPUs]] implemented in [[SSI]] [[Schottky TTL]] logic.
  
The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were configured with high-speed MOS or bipolar memory, respectively, on a special bus which was part of the CPU's [[backplane]].
+
(The difference between the two was whether they worked with the [[FP11-B Floating-Point Processor|FP11-B]] or [[FP11-C Floating-Point Processor|FP11-C]] [[Floating point processor|FPP]].)
  
Optionally, the machine could be configured with a KT11-C memory management unit; the FP11 floating-point processor was also optional.
+
The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were configured with high-speed [[Metal Oxide Semiconductor|MOS]] or [[bipolar]] [[main memory|memory]], respectively, on a special [[bus]] which was part of the CPU's [[backplane]].
 +
 
 +
Optionally, the machine could be configured with a [[KT11-C Memory Management Unit]]; the [[FP11 Floating-Point Processor]] was also optional.
  
 
The machine had an 18-bit UNIBUS, allowing it to address 256KiW of memory.
 
The machine had an 18-bit UNIBUS, allowing it to address 256KiW of memory.
 
== KB11-A CPU ==
 
 
The KB11-A board set included:
 
 
* M8100 Data and Address Paths
 
* M8101 General Register and Control
 
* M8102 Instruction Register and Decode
 
* M8103 ROM and ROM Control
 
* M8104 Processor Data and UNIBUS Registers
 
* M8105 Timing and Miscellaneous Control
 
* M8106 UNIBUS and Console Control
 
* M8109 Timing Generator
 
 
In addition, the CPU includes either:
 
 
* M8116 Segmentation Jumper Board
 
 
used when the KT11-C memory management unit is not present, or:
 
 
* M8107 Segmentation Address Paths
 
* M8108 Segmentation Status Registers
 
 
which comprise the KT11-C.
 
 
== KB11-D CPU ==
 
 
The KB11-D board set included many of the same boards as the KB11-A, with the following differences:
 
 
* The M8102 Instruction Register and Decode was replaced with the M8132
 
* The M8103 ROM and ROM Control was replaced with the M8123
 
* The M8106 UNIBUS and Console Control was replaced with the M8119
 
 
When the KT11-C memory management unit (termed the KT11-CD in this CPU) was present, the M8108 Segmentation Status Registers board of the KB11-A was replaced with the M8108-YA variant.
 
  
 
== hampage.hu ==
 
== hampage.hu ==
 
Quoting:
 
Quoting:
 
<i>
 
<i>
Introduced two years after the [[PDP-11/20]], in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.
+
Introduced two years after the [[PDP-11/20]], in June 1972. The KB11 was a faster, [[microcode]]d CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.
  
The cycle time of the [[PDP-11/45]] with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.
+
The cycle time of the PDP-11/45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.
  
The [[PDP-11/50]] was basically the same machine with different memory. The [[PDP-11/55]] ([[KB11D]]) used the modified CPU of the [[PDP-11/70]], where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.
+
The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the [[PDP-11/70]], where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.
 
</i>
 
</i>
  

Revision as of 01:01, 30 April 2018

A PDP11-45


PDP-11/45
Manufacturer: DEC
Architecture: PDP-11
Year Introduced: June 1972
Form Factor: minicomputer
Word Size: 16 bit
Design Type: microcoded
Physical Address Size: 18 bit
Virtual Address Size: 16 bit
Bus Architecture: UNIBUS/FastBus


The PDP-11/45 was the early fast UNIBUS PDP-11 system, using the KB11-A CPU (early units, prior to 1976) or KB11-D CPU (later units), high-performance CPUs implemented in SSI Schottky TTL logic.

(The difference between the two was whether they worked with the FP11-B or FP11-C FPP.)

The PDP-11/50 and PDP-11/55 were systems which used the exact same processor, but were configured with high-speed MOS or bipolar memory, respectively, on a special bus which was part of the CPU's backplane.

Optionally, the machine could be configured with a KT11-C Memory Management Unit; the FP11 Floating-Point Processor was also optional.

The machine had an 18-bit UNIBUS, allowing it to address 256KiW of memory.

hampage.hu

Quoting: Introduced two years after the PDP-11/20, in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.

The cycle time of the PDP-11/45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.

The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the PDP-11/70, where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.

Documentation

Gallery

A PDP-11/55 setup Different view of the PDP-11/55 setup The frontpanel was even nicer than the /20's. A really wonderful picture of the frontpanel (thanks to Csaba Tóth!) A nice configuration The "mysterious" PDP-11/45 11/45 at the Technical University of Budapest: in the foreground you can see a Videoton VDT52100 (VT52-compatible) terminal.