It used a multi-port memory version of the MK11 memory system, the MKA11. Some devices, such as disks and magnetic tape drives, could be shared between two of the CPUs, using the multi-port capabilities of many MASSBUS devices; other devices (e.g. UNIBUS devices) could not be shared (other than via software, or use of a UNIBUS switch).
The CPU was the KB11-E CPU, a modified version of the KB11-C CPU of the -11/70. An Interprocessor Interrupt (IIST) facility in each CPU, interconnected over a private bus, allowed one CPU to interrupt or bootstrap another CPU. A multi-ported high-resolution 'Time of Day' clock was also provided. Also, the ASRB instruction was modified to be atomic, for synchronization between CPUs.
There was also a planned Commercial Instruction Set processor, the CISP.
A significant run of prototypes were produced, and the RSX-11 operating system was enhanced to support multi-processor operation. The -11/74 was cancelled, however (reputedly because of concern that with its very high I/O bandwidth, it would compete with the new VAX-11/780), and never appeared as a product.
|v • d • e PDP-11 Computers and Peripherals|
| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70|
PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94
Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FIS floating point • FP11 floating point • PDP-11 Commercial Instruction Set • PDP-11 Memory Management • PDP-11 stacks • PDP-11 family differences