PDP-8/E

PDP-8/E
PDP-8/E front panel
Manufacturer:	DEC
Architecture:	PDP-8
Year Introduced:	1970
Form Factor:	minicomputer
Word Size:	12
Logic Type:	TTL
Design Type:	clocked random logic
Clock Speed:	385KHz
Memory Speed:	1.2 μseconds
Physical Address Size:	32KW (requires optional KM8-E)
Virtual Address Size:	4KW
Memory Management:	bank selection, CPU mode
Bus Architecture:	OMNIBUS
Operating System:	OS/8, TSS/8
Predecessor(s):	PDP-8/I
Successor(s):	PDP-8/A
Price:	US$5K (CPU and 4KW memory)

The PDP-8/E was an improved model in the PDP-8 line, and introduced the OMNIBUS for interfacing to device controllers.

The PDP-8/F was a cost-reduced version of the -8/E with the same CPU and core main memory, but only a single OMNIBUS backplane. The PDP-8/M is the OEM version of the PDP-8/F.

The -8/E's KK8-E CPU consists of five quad boards; the MM8-E core memory that was standard on the -8/E consisted of sets of three quad boards.

Options included:

• KA8-E Positive I/O Bus Interface, to allow use of older PDP-8 devices
• KM8-E Memory Extension and Time-Share Option, which was needed to support more than 4K words of memory, and allowed the computer to operate in either Executive Mode or User Mode
• MP8-E Memory Parity
• KD8-E Data Break Interface
• KE8-E Extended Arithmetic Element, which supported hardware integer multiplication and division, one-bit double-word shifts, and normalization
• FPP12-P and FPP12-AP Floating Point Processor (24+12 bits)
• FPP12-AE Double Precision option (FPP12-AP only, 60+12 bits)

It could perform an addition to the accumulator in 2.6 μseconds, and a 12 by 12 bit multiplication with 24 bit result in 40 μseconds, using the math extension hardware.

The -8/M could be supplied with either a KC8-M Operator's Console, or a KC8-ML Programmer's Console, the latter being basically identical to the KC8-EA Programmer's Console of the basic -8/E.

Images

External links

• First-Hand:PDP-8/E OMNIBUS Ride - PDP-8/E Design Story
• Digital PDP-8F
• PDP-8/M Restoration Project