QBUS

The QBUS, also called the LSI-11 Bus (from its introduction in the LSI-11), was intended as a cheaper alternative to the UNIBUS general system bus from DEC. It was widely used in later PDP-11s and smaller VAXen.

While similar to the UNIBUS, both at a high level, in that it supported both main memory and peripheral controllers through read-write cycles, DMA, and interrupts, as well as in much of the low-level detail, such as being entirely asynchronous, and using the same driver chips for its wired-OR transmission lines, it differed in a number of ways.

The biggest difference was that it used multiplexed address and data lines (to reduce the pin count), as opposed to the separate address and data lines of the UNIBUS. Another was that although it also supported 4 levels of interrupt priority, that support was optional, and used a more complex signalling mechanism, with only a single shared bus grant line, to do so. Later in its life, the QBUS added support for block transfers, to increase the transfer rate of the bus.

Signalling

Like the UNIBUS, there are three basic kinds of cycles on the QBUS: data read/write cycles (in which a 'master' reads or writes data to/from a 'slave', which is usually, but not always, memory); DMA cycles (in which a device gains control of the bus so that it can do an identical read/write cycle); and interrupt cycles, in which a device causes the CPU to perform an interrupt.

Also like the UNIBUS, all QBUS transactions are asynchronous, and use interlocked request/response signals for control and timing; also, most QBUS signal lines are electrically bi-directional transmission lines (even though some of these are logically uni-directional); only the grant lines (BDMG and BIAK) are physically uni-directional, and are wired in a daisy-chain fashion.

Read/write cycles come in the same basic forms as on the UNIBUS: DATI for word reads, DATO for word writes, DATIO for word read-modify-write cycles, and DATOB and DATIOB for byte write/R-M-W cycles. On the UNIBUS, however, two control lines coded the cycle type; on the QBUS, discrete control lines exist for each type of cycle (BDIN and BDOUT, along with BWTBT).

Like the UNIBUS, bus lines are normally held at a high voltage by the terminator, and driven low to assert them; unlike the UNIBUS, on which bus grants are positive-going pulses, QBUS grants are also asserted negative.

Device addressing

To reduce the number of gates needed on devices to decode their addresses, the QBUS includes a special signal, BBS7, to indicate a reference to the device registers in the 'I/O page' of the bus address space. Devices need to look at only this signal and address lines 0 through 12 to recognize their address(es). (Some QBUS CPUs do not even drive the high address lines during references to the I/O page.)

Block transfers

The QBUS later added block transfer modes, DATBI and DATBO; in block mode, the address is sent only once in a group of cycles, thereby nearly doubling the transfer rate of the bus. Only later models of main memory (slaves) and devices (DMA masters) support this mode. The bus line BBS7 is 'recycled' (at a later portion in the cycle than its normal use) to request a block transfer; the bus line BREF (used for external refresh of MOS memory), which had by that time fallen into desuetude, was re-purposed to allow a memory to signal that it supported block mode.

Interrupts

On the QBUS, multi-level priority interrupts share a single grant line; to do this, interrupt-requesting devices must monitor the higher-priority request lines, and refrain from intercepting a grant if there is a higher-priority request pending. Early QBUS devices did not implement this multi-level priority scheme.

Parity

The bus BDAL17 line is driven during the data read phase of a read cycle to indicate that the addressed entity (usually main memory) implements parity or some other error detection system (e.g. ECC). If BDAL16 is asserted, that indicates that an error has occurred.

Backplanes

QBUS backplanes come mainly in two physical types, dual and quad. The QBUS itself is fully carried in a dual slot, and the quads are further sub-divided into two types, the so-called Q/Q and Q/CD.

In quad Q/Q backplanes, both sides of each quad slot are fully wired for QBUS, and so a single slot can hold two separate dual-width QBUS devices. The device locations are usually arranged for grant priority in so-called 'serpentine' order, i.e. one with the devices in the following kind of order (facing the backplane from the board side):

1-2
4-3
5-6
8-7
9-10

etc.

In a quad Q/CD backplane, the CD connectors form a private bus, sometimes called the CD interconnect, used to connect together board pairs. (The CD connectors run down the right-hand side, when facing the side of the backplane where the boards plug in, with the CPU at the top.)

NOTE WELL: For reasons which seem utterly incomprehensible, many boards designed for Q/CD slots (such as PMI cards) do not avoid the QBUS pins on the CD connectors which contain 'hazardous' (to TTL circuitry) voltages. [NOTE: The exact failure mode here is still not understood; the PMI spec was examined, but no clash of pin assignments was found. The warning is accurate, though: MicroNote 28 says "MSV11-J MODULES CAN[NOT] BE PLACED IN A Q/Q BACKPLANE SLOT. IF THIS IS ATTEMPTED PERMANENT DAMAGE WILL BE DONE TO THE BOARDS".] So, plugging such a card into a Q/Q backplane will generally destroy the card.

Variable address size

The QBUS was available in 16-, 18-, and 22-address-bit configurations (data width remained 16 bits in all three versions). The three versions are often referred to as Q16, Q18 and Q22.

CPUs, devices and backplanes all are one of the three alternatives; for instance, the earliest CPU, the LSI-11, is a Q16 device. Mixing cards and backplanes of differing address widths may, or may not, work; or may work, but with limitations - and may sometimes initially appear to work, but, when examined carefully, not work.

Important note: The 16-bit and 18/22-bit backplanes are electrically incompatible and mixing the two may damage cards on the bus.

One example of the kind of limitation that may occur happens when using a Q18 DMA device in a Q22 system. The device will function correctly, but can only do transfers to the lower 256KB of memory; software that uses this device will have to work around that limitation.

An example of something that looks like it might work, but does not in fact work, is mixing Q18 and Q22 memory cards in a Q22 system, with more than 256Kbytes of memory in total. The problem is that the Q18 memory card will respond at multiple places in the 22-bit address space; e.g. if a Q18 card is configured at address 0, it will also respond at 01000000.

It is possible to upgrade 18-bit backplanes to 22-bit; see Upgrading QBUS backplanes.

Pinout

QBUS pins are identified by the scheme used for the UNIBUS; there are two connectors, A and B; pins on the component side of the board are 1, those on the solder side are 2. Pins are identified by the 'DEC alphabet' (i.e. by A-V, with G, I, O and Q dropped).

By signal

Signal	Pin	Signal	Pin
Ground	AJ1	BDAL00	AU2
Ground	AM1	BDAL01	AV2
Ground	AT1	BDAL02	BE2
Ground	AC2	BDAL03	BF2
Ground	BJ1	BDAL04	BH2
Ground	BM1	BDAL05	BJ2
Ground	BT1	BDAL06	BK2
Ground	BC2	BDAL07	BL2
+5	AA2	BDAL08	BM2
+5	BV1	BDAL09	BN2
+5	BA2	BDAL10	BP2
+5B	AE1 *	BDAL11	BR2
+5B	AS1 *	BDAL12	BS2
+5B	AV1	BDAL13	BT2
+12	AD2	BDAL14	BU2
+12	BD2	BDAL15	BV2
+12B	AS1 *	BDAL16	AC1
+12B	BS1	BDAL17	AD1
-12	AB2	BDAL18	BC1
-12	BB2	BDAL19	BD1
		BDAL20	BE1
ASpare2	BU1	BDAL21	BF1
MSpareA	AK1
MSpareB	AL1	BBS7	AP2
MSpareB	BK1	BDIN	AH2
MSpareB	BL1	BDOUT	AE2
PSpare1	AU1	BREF	AR1
PSpare2	BU1	BRPLY	AF2
PSpare4	BS1	BSACK	BN1
SSpare1	AE1 *	BSYNC	AJ2
SSpare2	AF1	BWTBT	AK2
SSpare3	AH1 *	BDMGI	AR2
SSpare8	BH1	BDMGO	AS2
		BDMR	AN1
BDCOK	BA1	BIAKI	AM2
BEVNT	BR1	BIAKO	AN2
BHALT	AP1	BIRQ4	AL2
BINIT	AT2	BIRQ5	AA1
BPOK	BB1	BIRQ6	AB1
SRUN	AH1 *	BIRQ7	BP1

Signals marked with a "*" show cases where two signals use the same pin (not at the same time, obviously).

By pin

Signal	Pin	Note	Signal	Pin	Note
BIRQ5	AA1	old BSpare1	+5	AA2
BIRQ6	AB1	old BSpare2	-12/-5	AB2
BDAL16	AC1	old BSpare3	Ground	AC2
BDAL17	AD1	old BSpare4	+12	AD2
SSpare1	AE1	alt +5B	BDOUT	AE2
SSpare2	AF1	alt SRUN/SMENBL on CF1	BRPLY	AF2
SSpare3	AH1	alt SRUN on CH1	BDIN	AH2
Ground	AJ1		BSYNC	AJ2
MSpareA	AK1		BWTBT	AK2
MSpareB	AL1		BIRQ4	AL2	was BIRQ
Ground	AM1		BIAKI	AM2
BDMR	AN1		BIAKO	AN2
BHALT	AP1		BBS7	AP2
BREF	AR1		BDMGI	AR2
+5B/+12B	AS1	old PSpare3	BDMGO	AS2
Ground	AT1		BINIT	AT2
PSpare1	AU1		BDAL00	AU2
+5B	AV1		BDAL01	AV2
BDCOK	BA1		+5	BA2
BPOK	BB1		-12/-5	BB2
BDAL18	BC1	old SSpare4	Ground	BC2
BDAL19	BD1	old SSpare5	+12	BD2
BDAL20	BE1	old SSpare6	BDAL02	BE2
BDAL21	BF1	old SSpare7	BDAL03	BF2
SSpare8	BH1		BDAL04	BH2
Ground	BJ1		BDAL05	BJ2
MSpareB	BK1		BDAL06	BK2
MSpareB	BL1		BDAL07	BL2
Ground	BM1		BDAL08	BM2
BSACK	BN1		BDAL09	BN2
BIRQ7	BP1	old PSpare6	BDAL10	BP2
BEVNT	BR1		BDAL11	BR2
PSpare4/+12B	BS1		BDAL12	BS2
Ground	BT1		BDAL13	BT2
PSpare2	BU1		BDAL14	BU2
+5	BV1		BDAL15	BV2

References to pin "Cxy" or "Dxy" refer to a quad-wide slot (e.g. as used by the original LSI-11 CPU board).

See also

• DMA Request and Grant
• CD interconnect
• Private Memory Interconnect
• LSI-11 Bus interface chips
• Bus Arbitration on the Unibus and QBUS
• QBUS backplanes
• QBUS processors
• QBUS memories
• QBUS devices

Further reading

• Microsystems Handbook (1985), Supermicrosystems Handbook (1986) - Documents block mode (in Appendix A, "Q-bus")

External links

• MICRO/PDP-ll Handbook - Appendix E: LSI-11 BUS Technical Specifications (pp. 255-301)