Difference between revisions of "RH11 MASSBUS controller"
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The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B'). | The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B'). | ||
| − | If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] grants. A jumper allows the RH11 to do block transfers on UNIBUS 'B' without going through an arbitration cycle. | + | If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] grants. A jumper allows the RH11 to do block transfers on UNIBUS 'B' without going through an arbitration cycle; the 'A' UNIBUS has a mode where it does two DMA cycles per grant. |
==Registers== | ==Registers== | ||
Revision as of 14:28, 28 July 2018
The RH11 MASSBUS controller allowed the interconnection of MASSBUS devices such as the RP04 to systems with a UNIBUS, primarily PDP-11's.
The RH11 has the capability to operate in 18-bit mode; in this mode (used in the UC15 UNICHANNEL-15 on the PDP-15), the PA and PB UNIBUS lines are used for data bits 16 and 17.
Second UNIBUS
The RH11 contains connectors and circuitry for two separate UNIBUSes; the second UNIBUS is primarily used on systems with multi-port memory, such as the PDP-11/45.
The registers in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, interrupts of the CPU are only possible via UNIBUS 'A'. The RH11 can be set under software control to do DMA data transfers on either the first or second UNIBUS (UNIBUS 'B').
If no CPU is connected to UNIBUS 'B', an M9300 terminator at the start of the bus can be configured to do NPR grants. A jumper allows the RH11 to do block transfers on UNIBUS 'B' without going through an arbitration cycle; the 'A' UNIBUS has a mode where it does two DMA cycles per grant.
Registers
The RH11 contains 4 registers, plus a share of a fifth; they are
- RHCS1 - Control and Status 1 (shared)
- RHWC - Word Count
- RHBA - Bus Address
- RHCS2 - Control and Status 2
- RHDB - Data Buffer (for maintenance)
As is standard for the MASSBUS, all the other device registers are in the device.
Hardware
The RH11 consisted of a double system unit backplane into which plugged a number of cards:
Two of them hex-sized:
- M7294 - DBC - Data Buffer and Control
- M7295 - BCT - Bus Control
Two dual-sized cards containing controller logic:
- M7296 - CSR - Control and Status
- M7297 - PAC - Parity Generation and Checking
Three dual-height M5904 MASSBUS transceiver modules.
Optionally one or two (see below) single-height cards:
- M688 - UNIBUS Power Fail Driver
The RH11 backplane also contained three SPC slots in otherwise-unused slots.
