SS-50 bus

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The SS-50 bus was created in 1975 by SWTPC for their 6800 computer. Other manufacturers started producing boards for this bus too. Later SWTPC modified the bus to for their 6809 version of the SWTPC computer. This variant is sometimes, but not always, referred to as SS-50C. And there is also a version with 20 address lines instead of the 16 in the original. It was designed for paged-memory 6809 systems.

This table describes the signals of the various version. Underscore (e.g. D0) is used to indicate a complemented or inverted signal, as the more common way of using a horisontal line above the signal doesn't seem to be available in mediawiki.

Line Function
SS-50 SS-50C SS-50 S/09
1 D0 D0 D0
2 D1 D1 D1
3 D2 D2 D2
4 D3 D3 D3
5 D4 D4 D4
6 D5 D5 D5
7 D6 D6 D6
8 D7 D7 D7
9 A15 A15 A15
10 A14 A14 A14
11 A13 A13 A13
12 A12 A12 A12
13 A11 A11 A11
14 A10 A10 A10
15 A9 A9 A9
16 A8 A8 A8
17 A7 A7 A7
18 A6 A6 A6
19 A5 A5 A5
20 A4 A4 A4
21 A3 A3 A3
22 A2 A2 A2
23 A1 A1 A1
24 A0 A0 A0
25 GND GND GND
26 GND GND GND
27 GND GND GND
28 +8V +8V +8V
29 +8V +8V +8V
30 +8V +8V +8V
31 -12V -12V -12V
32 +12V +12V +12V
33 INDEX INDEX INDEX
34 M RESET MRDY MRDY
35 NMI BSY NMI/BSY
36 IRQ IRQ IRQ
37 UD2 FIRQ FIRQ
38 UD1 Q Q
39 φ2 E E
40 VMA VMA VMA
41 R/W R/W R/W
42 Reset Reset Reset
43 BA BA BA
44 φ1 BS BS
45 HALT HALT HALT
46 110b BREQ / 110b BREQ
47 150b 9600b A19
48 300b 300b A18
49 600b 4800b A17
50 1200b 1200b A16

Notes:

  • Verification is still needed for some of these signals!
  • D0 - D7: Data Bus: The SS-50 data bus is the complement of the 6800 data bus lines D0-D7. These lines are bidirectional.
  • R/W: Read/Write: The read/write line of the processor. When it is high, D0-D7 are inputs to the CPU, when low D0-D7 are outputs from the CPU.
  • A0-A15: Address bus: Address bus of the CPU.
  • A16-A20: Address bus extension (S/09 only): Used by bank switching or paged memory systems to address up to 1MB of memory
  • VMA: Valid Memory Address: The complemented 6800 VMA line. Goes low when a valid address has been placed on the address bus.
  • M RESET: Manual Reset: This pin is the input to a one-shot multivibrator. When pulled low by e.g. pressing a reset button, the one-shot pulses the Reset line which resets the system
  • Reset: Reset: The reset line is the output of the one-shot triggered either by M RESET or automatically on system power up. It is connected to the reset input of the processor, and to other resettable pheripherals.
  • NMI: Non-maskable interrupt: >ctive low line connected to the processor's NMI input.
  • BUSY: Busy: (-C and -S09 only)
  • IRQ: Interrupt Request: Active low line connected to the processor's IRQ input.
  • HALT: Halt: Active low line connected to the processor's HALT input. The 6800 halts the execution and floats the address and data buses and the R/W line. External devices can then access memory for DMA, for example
  • BA: Bus Available: This is the BA output of the processor. Goes high in response to a Halt input, to signal that buses are available (floating)
  • φ1: The Phase 1 output from the two-phase non-overlapping clock of the processor
  • φ2: The inverted Phase 2 output from the two-phase non-overlapping clock of the processor, used to indicate the presence of valid data on the data bus
  • UD1, UD2: User Defined: User defined lines are not assigned pre-defined functions.
  • 110b,150b,300b,600b,1200b: Serial clock: Outputs of a crystal-controlled baud rate generator, may be used by a serial interface peripheral
  • 4800b,9600b: Serial clock: (-C only)
  • GND: Ground lines
  • +8V: Power: Unregulated +8V, may be used by on-board regulators to create +5V, for example
  • -12V: Power: Regulated -12V
  • +12V: Power: Regulated +12V
  • INDEX: No pin: Physically plugged to prevent incorrect insertion of a board
  • MRDY: Memory Ready: (-C and -S/09 only)
  • BSY: Busy (-C and -S/09 only)
  • FIRQ: Fast Interrupt Request: (-C and -S/09 only)
  • BREQ: Bus Request: (-C and -S/09 only)
  • Q: Quadrature Clock Signal: (-C and -S/09 only)
  • E: Another clock signal: (-C and -S/09 only>