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- ...ranging from 1 to 4, depending on the number of [[Central Processing Unit|CPUs]] in the system. They shared much of their cabinetry and components with the [[DEC Alpha|Alpha]]-based [[10000 AXP series]] systems as well as the VAX 7000 se2 KB (214 words) - 15:28, 23 May 2024
- ...000 series]], and also used in other later [[Digital Equipment Corporation|DEC]] computers. ...s the bus interfaces considerably. The large [[cache]]s on the 7000 series CPUs made this tradeoff reasonable. The LSB is [[pipeline]]d, though; this allow3 KB (396 words) - 01:44, 8 May 2024
- ...documentation gives the expansion of 'NMI'). The [[Central Processing Unit|CPUs]], [[main memory]] and [[input/output|I/O]] adapters (called 'NBIs') all co ...oughout, organized in [[synchronous]] logic. (In dual-CPU systems, the two CPUs run off a common [[clock]].)8 KB (1,158 words) - 03:12, 23 May 2024
- Wed Dec 31 19:02:20 EST 1969 Wed Dec 31 19:32:43 EST 196933 KB (4,919 words) - 12:31, 21 June 2023
- [http://bitsavers.org/pdf/dec/pdp10/TOPS20/V7/MGR_GUIDE.MEM.txt TOPS-20 System Manager's Guide June 1990 explains in detail how the '''Common File System''' (CFS) works on the [[DEC]] [[PDP-10]], [[DECSYSTEM-20]] computer running the [[TOPS-20]] operating s53 KB (6,770 words) - 13:15, 16 November 2023
- The MCA20 consists of 6 [[DEC card form factor|hex]] cards, of 3 types: ...here (including on the M8513 Cache Control card), and included in all KL10 CPUs.3 KB (490 words) - 18:09, 14 November 2023
- The '''M-bus''' from [[Digital Equipment Corporation|DEC]] was a unique [[synchronous]] [[bus]] used in some [[VAXstation]]s. It sup ...tent data. The M-bus also supported [[interrupt]]s from [[peripheral]]s to CPUs. It used [[parity]] for [[error detection]].862 bytes (120 words) - 14:10, 15 January 2024
- | Revision levels are tracked according to DEC Standard 068.... | Part revisions are tracked according to DEC Standard 012 conventions. Each part has an alphanumeric revision, up to a198 KB (5,881 words) - 23:03, 28 March 2024