Laser System Bus
It supports multiple processors and multiple main memory memory modules; a single I/O port module uses a special slot. The overall system built around an LSB thus forms a tightly-coupled multi-processor. The bus has special capabilities to support the shared access to memory required by such a system, including support for cache coherency.
The LSB is of limited length, is synchronous (all parts of the transfer occur at fixed temporal offsets from the arbitration cycle which allocates the bus to a particular master), and has distributed arbitration (individual bus request lines run from each module connected to the bus to every slot in the backplane). Arbitration and data transfers use logically separate divisions of the bus, so they can occur in parallel.
It is also 'non-pended', which means that an operation cannot be left in an incomplete state, to allow other entities to use the bus, before resuming, and finishing. This does not allow highly efficient use of the bus bandwidth, but simplifies the bus interfaces considerably. The large caches on the 7000 series CPUs made this tradeoff reasonable. The LSB is pipelined, though; this allows up to three transfers to be in progress at any time.
The LSB has 128 signal lines; data and addresses are multiplexed onto the same set of lines. LSB addresses are 40 bits, giving an address space of 1 terabyte. Address and control information are protected with parity; memory data is protected with an ECC.
All memory transfers on the LSB are 64 bytes in length. It has a 20 ns bus cycle; a complete operation lasts for 17 cycles. The maximum data rate is 800 MB per second; of this, 640MB per second could be utilized.
- DEC 7000/10000 AXP, VAX 7000/10000 Platform Technical Manual (EK-7000A-TM.001) - the LSB bus is covered in Chapter 2 (pp. 21-78 of the PDF)
- Technical Description of the DEC 7000 and DEC 10000 AXP Family, in Volume 4 Number 4 - the LSB is covered on pp. 103-105 of the PDF of this issue of the Digital Technical Journal