Talk:MB20 core memory
Basically you start access on the first word, then while you read the first word, the memory controller starts access on the second word, and while you read the second word, the memory controller starts access on the third word,
Now, depending on burst length, like 8 words, you can restart access on the first word again, while you are reading the fourth word, and start the cycle over again, until you reach the length of the burst length.
The iPX 420 did bit interleaving. the 8088 did byte interleaving, ( 8bit processor 1 word interleaving. ) the 8086 also did byte interleaving, the 286 did word interleaving, two bytes at a time, the 386 did word interleaving, 4 bytes at a time, but it had to start on a 4 word boundry for the first read.
- Err, I do actually know about interleaving (worked on machines that used it, back in the day); that "still trying to understand interleaving" really meant 'still trying to understand the interleaving on the MB20'.
- BTW, what you've described isn't really interleaving (in the classical sense of that term); not sure of the exact term for the above, it's kind of like pipelined multi-word block reads. Interleaving is when you have two (for 2-way interleaving) separate memory controllers (each with an associated block of storage), and reads to location N and N+1 each go to different controllers. This is useful for core memory, since it's destructive readout (i.e. on read, the data has to be written back), so the cycle time is considerably longer than the access time. (And now that I look, the interleaving article doesn't include that bit about why the cycle time is longer for core, I'll have to add it.) Jnc (talk) 15:15, 21 March 2019 (CET)