Core memory

From Computer History Wiki
Jump to: navigation, search

Core memory is a form of main memory that uses tiny rings of magnetic material ('cores', hence the name) to store data; magnetized in one direction, such a core represents a '1', and in the other, a '0'.

Core memory was a key breakthrough in the development of computers. Prior to its invention, all forms of main memory had been clumsy and expensive (per bit): cathode ray storage tubes, acoustic delay lines, etc. In addition to being inelegant, they had other issues: it was difficult to make large memories out of them, and most had additional issues (e.g. delay lines could have slow access times).

Core memory solved all these problems. It was reliable, cheap, relatively compact, fast - everything that one could want of a main memory. It is difficult to convey just how much better core memory was than its predecessor main memory technologies.

Before the invention of core memory, there were only a few computers, with extremely small main memories. By the time core finally became obsolete, two decades after its introduction, computers (albeit not personal computers) had become ubiquitous. It is no understatement to say that core memory made the computer age possible.

At the very start, it was somewhat expensive to fabricate, since early core memory was assembled by hand, but various companies (principally IBM) produced machinery to produce core memory, radically lowering the price.

Technical details

The ability of a ring of magnetic material to store a bit by being magnetized had long been known, from work with them in transformers. A wired around (or through, as was eventually used) the core could be used to magnetize it in one direction or another, by running a sufficiently large pulse of current through the wire. The problem was how to create large memories using this basic mechanism.

The answer was the invention of the so-called 'coincident core' concept, in which an two-dimensional array of cores (a 'plane') had a wire strung through the cores along each horizontal, and also along each vertical axis; thus, each core has two wires through it, one 'X', and one 'Y'.

A current pulse of 1/2 the required size to switch the magnetization (the so-called 'half-select current') is sent through a selected X axis wire, and also through a selected Y axis wire; only at the one core where both those X and Y wires pass through it do the two pulses add up to a large enough current to 'flip' the magnetization of that core.

A third wire is also needed, the so-called 'sense' wire, which allows the memory circuitry to detect what the prior value stored in a particular core was. Core memory is 'destructive readout', in that to read the value stored in a particular core, it is written to '0'; in so doing, a different current will be induced in the sense wire, depending on whether the previous value stored in the core was 0 or 1.

The destructive nature of the readout does mean the data has to be written back afterwards, but clever designers soon learned to make use of this; for instance, if an instruction wants to increment a particular location in main memory, the location can be read out, with the CPU telling the memory to wait for the CPU to tell it what value to write back.

Since with coincident core setup, only the selected core will flip to 0, a single sense wire can be run through all the cores in a plane, thereby significantly reducing the wiring/circuit complexity.

The core array of X*Y cores notionally needs X + Y drivers (in reality, various switching tricks allow use of far less than that many) - but note that adding two drivers, one X and one Y, allows use of four times as many cores; like the later DRAM which replaced core, as the memories became larger, they became more efficient.

Finally, to produce Z-bit wide words, one provided Z core arrays in parallel. One additional piece of complexity appears when this is done. Typically, the same X and Y lines are sent in parallel to each core plane. This is fine for reading, when all the bits in a particular word are read; but for writing, when some bits need to be set to 0, and others to be 1, it is problematic.

The solution is the so-called 'inhibit' line, another line through the core; for bits which are to be left as 0 (remember that reading will set the cores to 0), a 1/2 current will be sent through the inhibit line in the reverse direction, which produces an 'anti-pulse' which prevents the core from being written to 1. Like the sense line, a single inhibit line can be run through all the cores in particular array.

Early cores were fairly large (several millimeters in diameter), and thus required a lot of current, and time, to switch. Over time cores became so small that it was almost impossible to see the holes without magnification, thereby increasing their speed, and decreasing their energy usage.

Eventually, core designers realized that the sense line was only used during reading, and the inhibit during writing, so later core memories combined both functions into a single wire, reducing the number of wires needed to run through each core from four to three. With the smaller cores, this was a big help.