KA11 changes for the KT11-B

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The KT11-B Paging Option for the PDP-11/20 involves some modifications to the KA11 CPU. Those changes are documented in a DEC print set, 7605961-0, "Central Processor for KT11-B".

The following prints are included in the "Central Processor for KT11-B" set:

Drawing Sheets Title
D-CS-7605961-0-3 3 State Control - M727 K2
D-CS-7605961-0-4 3 Priority - M824 K3
D-CS-7605961-0-5 5 Bus Interface & Instruction Register - M725 K9
D-CS-7605961-0-6 4 Instruction Register Decode - M726 K10
D-CS-7605961-0-7 3 Flag Control - M822 K12
D-CS-7605961-0-8 4 Bus & Console Control - M724 K13
D-BS-7605961-0-9 1 KA11 to KT11 Interface
D-AP-7605961-0-10 1 PC Board Modifications
D-WS-7605961-0-11 1 KA11 Mods for use with KT11-B

KA/KT Interface

The KA11 and KT11-B are connected by a UNIBUS between them (which carries all the CPU's normal bus functions, such as memory cycles), and also by an additional cable. That cable carries various other signals, mostly internal signals of the KA11 which are used by the KT11-B (along with a few additional ones which are synthesized specially), although there are a few signals from the KT11-B, used in the modified KA11.

On the KT11 end, the cable plugs into slot D12, and on the KA11 end, into slot B09. The cable pinout is:

Pin Source Signal  ! Pin Source Signal
A1 - Ground A2 - Unused
B1 KA11 Odd address error B2 - Unused
C1 - Ground C2 - Ground
D1 KT11 PGC 04 D2 KA11 RTS
E1 KA11 DEST E2 KA11 CLKT
F1 - Ground F2 - Ground
H1 KA11 SOURCE H2 KA11 -TRAPS
J1 KA11 ISR 12 J2 - Ground
K1 - Ground K2 KA11 SERVICE
L1 KA11 ISR 7 L2 - Ground
M1 KA11 -RTI M2 KA11 TIME OUT
N1 - Ground N2 - Ground
P1 KA11 JSR P2 KA11 FETCH
R1 - Ground R2 - Ground
S1 KT11 CLK NPR S2 KA11 TRAP
T1 - Ground T2 KA11 [ST+SR] K13-3
U1 - Unused U2 - Ground
V1 - Unused V2 KT11 Force timeout

(Signals partially in lower case are not formal names from the prints, but give a sense of what the signal does.)

KA11 changes

The changes to the KA11 include a small number of modifications to several boards in the KA11 (below), and a number of changes to the wiring of the CPU backplane (also below).

An M138 FLIP CHIP (octal three-input NAND gates) is plugged into the KA11 backplane (in slot B08, otherwise unused), to provide additional gates, which are used to synthesize some of the signals sent across the KA11 - KT11-B interface cable. (Recall that slot B09 is where the interface cable between the KT11-B and KA11 plugs into the KA11.)

Board modifications

Alas, there is only one known set of the prints of the KT11-B changes to the KA11 - and that set is missing the page: "PC Board Modifications", D-AP-7605961-0-10. Luckily, there is apparently just enough duplicate information elsewhere (including a hand-modified set of KA11 prints, showing the changes to support the KT11-B) to allow it to be re-created.

The following are the changes on the three KA11 boards which are modified (KA11 backplane wiring changes are given in other sections below):

On the M824 Priority card, page K3-2:

  • The NAND gate (E24) feeding, via another NAND gate (also E24) the NPRF flop (E14) is re-purposed (as a NOR with inverting inputs):
    • Although one input (pin 5) remains connected to pin D12S1, that pin is now connected to K2-3 PERIF REL L
    • The other input (pin 4) is connected to the output of the NOR gate at the top of the page (E18, pin 1)
    • The output (pin 6) is used as an input to the next gate
  • A NOR gate is added between that gate, and the clear input of the NPRF flop; the 'KA11 mods' print set shows one gate used for this (E25, a 7402), but the hand-written mods to the standard KA11 prints show a different one (E10, a 7450)
    • In both prints, one input is connected to the output of the previous NAND gate
    • In the 'KA11 mods' print set, the other input is also connected to that signal; in the hand-modified set, that second input is connected to the '1' output of the NPRF flop (E14, pin 5)
    • The output is connected to the clear input of the NPRF flop (E14, pin 1)
  • The input of the NAND gate (E24, pin 2) which was being driven by the re-purposed NAND gate is now driven by the same signal as the other input (pin 1)

On the M822 Flag Control card, page K12-2:

  • The line in the upper right-hand corner between the output of the NAND gate (E28) and the preset input of the OVFLF flop (E15, pin 1) is deleted

On the M724 Bus & Console Control card, page K13-2:

  • The line from the E50 9601 timer low output (pin 6) to the clock input (pin 11) of the E46 Time-out flop is cut
  • A spare 7400 NAND gate (in E26), used as an OR with inverting inputs, has its output (pin 8) connected to the flop's clock input; its inputs are:
    • One input (pin 10) is connected to the timer high output (pin 8)
    • The other input (pin 9) is connected to backplane pin F06C1 ('FORCED TIMEOUT')

Wires removed

The following lists of wiring changes on the KA11 backplane give the content from print 7605961-0-11, "KA11 Mods For Use With KT11-B". All wires are listed as being 30 AWG.

Note: This print reproduced poorly, so there may be transcription errors (e.g. '8' for '3', etc). The goal is to eventually cross-check all this information with the prints, to verify all data, and supply that which is currently missing here. '?' indicates a currently un-readable character.

From To Signal Colour
B02T2 F08U2 K13-3 B MSYN H Orange
D12C2 D12S1 GND 12
E04K1 E07P2 K10-4 CLKT H
E03F1 E04L1 K?-2 SCLK L
D11B1 C06J1 K10-3 ODD ADRS ERR L
C06J1 D02N1 K10-3 ODD ADRS ERR L
D12S1 D12T1 GND 12 Brown

Wires added

All added wires are listed as Orange. This list had previously been checked, and annotated by hand in ink; those annotations are given here. All entries with no annotation given have a hand-written check-mark in ink. Text in italics are comments added during the transcription to this page.

From To Signal Comment
E03F1 F06H1 K1-2 SCLK L
D?2C2 D12T1 GND 12 None
D11B1 D02N1 K10-3 ODD ADDRS ERR L None
F04P2 B08A1 K10-2 ODD ADDRS ERR L
F04P2 B08B1 K10-2 ODD ADDRS ERR L
F04P2 B08C1 K10-2 ODD ADDRS ERR L
B08D1 B08E1 B08D1
B08D1 B08L1 B08D1
E03F1 B08M1 K1-2 SCLK L E04L1 - B08M1
B08J1 B08K1 B08J1
B08J1 C06J1 B08J1
B08N1 B09B1 B08N1
E04K1 B08P1 K10-2 CLKT H
E04K1 B08R1 K10-2 CLKT H
E04K1 B08S1 K10-2 CLKT H
B08U1 B08D2 B08U1
B08U1 B08F2 B08U1
B09D1 B08F1 D18 - PGC 04 (1) H
B09D1 B08H1 D18 - PGC 04 (1) H
B09D1 B08F2 D18 - PGC 04 (1) H
B08H2 B08J2 B08H2
B08H2 B0K2 B08H2 (Presumably 'B0K2' is a typo for 'B08K2')
B08H2 B08L2 B08H2
B08H2 E07P2 B08H2
D03T2 B08R2 K1-4 SERVICE H
E03L2 B08N2 K1-3 ISR (3+7) H None
B08S2 B08T2 B08S2
B08S2 B08U2 B08S2
B08S2 B08V2 B08S2
D11B2 B08P2 K12-3 TRAPS B02C1 - B08P2
F03J1 B09E1 K1-3 B DEST (0) H
F03M2 B09M2 K1-4 B SOURCE (1) H B09H1 - F11M2
E03R1 B09J1 K1-3 ISR 12 L
E03K1 B09L1 K1-3 ISR 7 L
F04S2 B09M1 K10-4 RTI H
C04D1 B09P1 K10-2 JSR H
B09S1 F02U2 D18 CLK NPR H
E04R1 B09D2 K10-3 RTS B09D2 - E11T2
D03P2 B09K2 K1-4 SERVICE L
F06M1 B09M2 K13-3 TIME OUT (0) H
F03J2 B09P2 K1-4 FETCH (0) H
C04P1 B09S2 K10-2 TRAP L
C06V1 B09T2 K13-3 -(ST+SR) H D06D2 - B11T2
B09V2 F06C1 D18 FORCE TIMEOUT H
B08V1 B09H2 B08V1
F02J1 D06D2 K2-3 CLR PTR L None
F02P1 D12S1 K2-3 PERIF REL L None
B12P2 B12V2 DEVICE 2+3 BG06
D11H2 E04L1 K1-2 R/W2 H
B08M2 B09E2 B08M2
F02J1 C06V1 K2-3 CLR PTR L Unlisted
(Not in original table; added by hand)
B09H1 F11M2 K1-3 ISR 12 L