KT11-B Major State circuitry
This is a detailed description of the the circuitry that generates the major state of the KT11-B (page 12-1, lower left corner) - and in particular, how the state change signals (XSHL, XSHR) work.
The four NOR gates on the right (drawn as AND gates with inverted inputs) generate four individual major state lines (XSR0-3) from two bits (the two D flops); the top flop is the 010 bit, and the bottom flop is the 01 bit.
(Note that this circuity is not a shift register, as per the Option Description Section 4.3; it can produce 4 different states from 2 bits, not possible with a shift register.)
Note that the D flops are drawn with the top (Q) outputs labelled '1' - this is because the outputs need to be inverted. So, logically speaking, the top output is 10(0) (i.e. when asserted, it means the high bit is 0), etc.
The four outputs (10(0), 10(1), 1(0) and 1(1)) are combined with XSHL and XSHR through an AND/OR network (actually all NANDS, so the un-named intermediate signals are logically inverted) which generates two signals, one for the D input of each flop:
- 10 flop: XSHR*1(1) + XSHL*1(0)
- 1 flop: XSHR*10(0) + XSHL*10(1)
(* = AND, + = OR; notation used throughout the KT11-B prints)
(Notice that this looks nothing like a conventional counter, where the new state of the high bit, after a count event, depends on the old state of the high bit as well as that of the low bit; these each depend only on the old state of the other bit.)
So, applying those functions to all the initial states, that produces the following table (initial state, flop inputs, new state):
So, a sequence of XSHL pulses will generate the following major state train:
00, 10, 11, 01, 00
and XSHR will produce:
00, 01, 11, 10, 00
Note that these are Gray-code sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.