- another block of synchronous circuitry, but using a clock which is not fixed relative to that of the destination (receiving) clock domain; or
- an asynchronous circuit.
Signals which pass across the boundary must be handled in such a way that they reliably appear to the circuitry inside the destination clock domain to be in one state or another. If the incoming signal and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), resulting in a race, that can produce meta-stability issues.
Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.
At a higher level, a synchronizer should result in a bit string passed across a clock domain boundary being the same on both sides.
One common way to implement a synchronizer is with two flip-flops in series, driven by a common clock from the destination clock domain. This allows the signal from the first flop (which is effectively 'sampling' the input) an entire clock period to settle out from any potential meta-stability, before it is passed on by the second flop; it does however mean that the signal undergoes significant real-time delay.
It is possible to describe a synchronizer as an arbiter where one of the input signals to the arbiter is the clock of the destination clock domain.
- Steve Golson, "Synchronization and Metastability", '2014 Synopsys Users Group Conference: SNUG Silicon Valley 2014', 2014 - Contains an excellent description of the problem
- Ran Ginosar, "Fourteen Ways to Fool Your Synchronizer", 'ASYNC '03: Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems', 2003, pp. 89-96 - An interesting discussion of synchronizers and synchronizer issues