View source for DR11-M general-purpose interface

[[Image:DR11-M.jpg|thumb|200px|right|DR11-M board]]

The '''DR11-M general-purpose interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, both output-only. It was a [[DEC card form factor|quad]] format card ('''M7865'''), and used an [[Small Peripheral Controller|SPC]] slot; it used [[programmed I/O]].

The DR11-M is roughly an output-only version of the earlier [[DR11-C general device interface]], but is not [[program compatible]] with the DR11-C.

Connection to the [[user]]'s device is via a pair of 40-[[pin]] [[Berg connector]]s; each is controlled by a separate set of [[register]]s (identical for the two connectors). Like the DR11-C, data going out to the user's device is latched in the DR11-M, so may be read at leisure.

==Configuration==

The device's [[register]] and [[interrupt vector]] [[address]]es are set by a pair of [[Dual Inline Package|DIP]] switches. Unusually for a UNIBUS device, its [[interrupt]] priority is also set by the switches. Both the vector and priority may be read in the Control and Status Register.

==Registers==

The device has two pairs of control and [[buffer]] registers, which can be configured to any four sequential [[word]] locations in the I/O page; the first DR11-M is normally configured to addresses 764000-76406:

{| border=1
! Register !! Abbreviation !! Address
|-
|Control and Status Register A || DRCSRA || 764000
|-
|Data Buffer Register A || DBDBRA || 764002
|-
|Control and Status Register B || DRCSRB || 764004
|-
|Datia Buffer Register B || DBDBRB || 764006
|}

In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.

===Control and Status Register (DRCSR)===
{{16bit-header}}
| ''SI'' || colspan=6 | ''Vector'' || SO || ''RQ'' || RQE || colspan=2 | ''Prority'' || ''DA'' || ''CID'' || ''DR'' || DRE
{{16bit-bitout}}

* SI - Status In: Signal from user's hardware which can be tested
* SO - Status Out: Signal to user's hardware
* RQ - Request: Signal from user's hardware which can be tested, or cause an interrupt 
* RQE - Request Enable: Allows setting RQ to cause an interrupt
* DA - Data Accepted: Monitors the Data Accepted In signal
* CID - CSR ID
* DR - Data Ready: Set by write to DBR to signal data has been latched, cleared by Data Accepted
* DRE - Data Ready Enable: Enables Data Ready Out to user's hardware

===Data Buffer Register (DRDBR)===
{{16bit-header}}
| colspan=16 | OUT15 <-> OUT0
{{16bit-bitout}}

[[Category:UNIBUS Peripherals]]