View source for DL10 PDP-11 Data Link

The '''DL10 PDP-11 Data Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).

On the PDP-10 side, it connected to the [[PDP-10 Memory Bus]], and also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style Memory and I/O [[bus]]ses (provided by the [[DMA20 Memory Bus Adapter]] and [[DIA20 IBus Adapter‎]] respectively).

On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.

The DL10 is used in the [[DN87 Universal Synchronous/Asynchronous Communications Front End Subsystem]].

There is little remaining DL10 documentation, alas; see below for links to what exists online.

==Data formats==

Note that the format is selected by the second octet in the word; the values used in that octet to select the byte size in the 'pointer' mode are disjoint from the values used in that octet for the other modes.

===Immediate mode===

{{36bit-header}}
| colspan=3 | Unused || colspan=3 | 0 ''or'' 7 || colspan=14 | Unused || colspan=16 | Data
{{36bit-bitout}}

===Indirect mode===

{{36bit-header}}
| A || colspan=2 | P || colspan=3 | 1 || colspan=8 | Unused || colspan=22 | Address
{{36bit-bitout}}

{| class="wikitable"
! A 
! Access
|- 
| 0 
| Read or write
|- 
| 1 
| Read only 
|}

{| class="wikitable"
! P
! 16-bit word position within 36-bit word
|- 
| 0
| Bits 0-15
|-
| 1
| Bits 16-31
|-
| 2
| Bits 20-35
|-
| 3
| Bits 2-17
|}

===Pointer modes===

{{36bit-header}}
| colspan=3 | P || colspan=3 | S || colspan=8 | Word count || colspan=22 | Address
{{36bit-bitout}}

Bytes are left-justified inside a 36-bit word.

{| class="wikitable"
! S
! Byte size
|- 
| 2
| 16
|- 
| 3
| 12
|- 
| 4
| 8
|- 
| 5
| 7
|- 
| 6
| 6
|}

==PDP-11 control and status registers==

DATO 100000 (Conditions out)
{{16bit-header}}
| Set 11 interrupt || Clear 11 interrupt || Set 10 interrupt || Clear 10 interrupt || Set nonex memory || Clear nonex memory || Set parity error || Clear parity error || Set word count overflow || Clear word count overflow || colspan=2 | || Error interrupt enable || 11 interrupt enable || colspan=2 | Interrupt assignment
{{16bit-bitout}}

DATI 100000 (Status)
{{16bit-header}}
| 11 interrupt || || 10 interrupt || || Nonex memory || ||  Set parity error ||  || Word count overflow || || This port enabled || || Error interrupt enable || 11 interrupt enable || colspan=2 | Interrupt assignment
{{16bit-bitout}}

==PDP-10 standard instructions==

CONO DLB,
{{36bithalf-header}}
| colspan=12 | Base address || colspan=4 | Mask for size of pointer block || colspan=2 | PDP-11
{{36bithalf-bitout}}

CONO DLC,
{{36bithalf-header}}
| Clear DL10 || Lock DL10 || Action of 1s ||| 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
{{36bithalf-bitout}}

CONI DLB,
{{36bit-header}}
| Diag || Diag msyn || Diag C0 || Diag C1 || Diag R2 || Diag R1 || Diag INH CYC || || 11-3 8K option || 11-2 8K option || 11-1 8K option || 11-0 8K option || IOC lock on || ~IOC lock delay on || ~IOC lock 1 out || ~IOC lock 0 out || 18-bit address || Standard interrupt || || Got DL10 locked || || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
{{36bit-bitout}}

==External links==

* [http://pdp-10.trailing-edge.com/bb-d549g-sb/01/boot11.mem.html BOOT11 - PDP-11 Bootstrap From PDP-10] - contains general description of the DL10 in section 4.0
* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-108OU-PD-002_KL10-Based_Physical_Description_Mar77.pdf KL10-Based Physical Description] - the DL10 is covered in Sections 1.8
* [http://bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-XSRMA-A-D%20DECsystem10%20System%20Reference%20Manual.pdf DECsystem-10 System Reference Manual] - documents the PDP-10's DL10 control instructions in Appendix C (on pp. 365-368 of the PDF)
* [http://www.bitsavers.org/pdf/dec/pdp10/periph/MP00068_DN87_Universal_Comm_System_Front_End_Jan76.pdf DN87 Field Maintenance Print Set] - contains complete engineering drawings for the DL10 (on pp. 100-212 of the PDF)

[[Category: PDP-10 Machine Interfaces]]
[[Category: UNIBUS Machine Interfaces]]