View source for DRV11-J High-Density Parallel Interface

[[Image:DRV11-J.jpg|thumb|200px|right|DRV11-J board]]

The '''DRV11-J High-Density Parallel Interface''' was a [[QBUS]] [[parallel interface]] [[device controller]] which provided four bi-directional 16-[[bit]] parallel ports. It was a [[DEC card form factor|dual]] format card (M8049). It used [[programmed I/O]]; the direction of each port was programmable. It was not [[program compatible]] with any other [[Digital Equipment Corporation|DEC]] parallel port controller.

Connection to the [[user]]'s device was via a pair of 50-[[pin]] [[Berg connector]]s; PORTS A and B through the bottom connector (furthest from the insertion handles), ports C an D via the top. Data going out to the user's device was latched in the DRV11-J, so may be read at leisure; data coming in from the user's device was merely sampled by the DRV11-J, so must be held until it has been read.

==Registers==

The device had four pairs of control and [[buffer]] [[register]]s, which could be configured to any eight sequential [[word]] locations in the I/O page. The first DRV11-J was normally configured to [[address]]es 764160-764176; the second to 764140-767756, the third to 764120-767736, and so on.

{| border=1
! Register !! Abbreviation !! Address
|-
|Control and Status Register A || DRCSRA || 764160
|-
|Data Buffer Register A || DRDBRA || 764162
|-
|Control and Status Register B || DRCSRB || 764164
|-
|Data Buffer Register B || DRDBRB || 764166
|-
|Control and Status Register C || DRCSRC || 764170
|-
|Data Buffer Register C || DRDBRC || 764172
|-
|Control and Status Register D || DRCSRD || 764174
|-
|Data Buffer Register D || DRDBRD || 764176
|}

<!-- In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.

===Status Register (DRCSR)===
{{16bit-header}}
| ''REQ B'' || colspan=7 | Unused || ''REQ A'' || INT ENB A || INT ENB B || colspan=3 | Unused || CSR1 || CSR0
{{16bit-bitout}}

* REQ B - Request B - Signal from user's hardware which can be tested, or cause an [[interrupt]] (below) 
* REQ A - Request A
* INT ENB A - Interrupt Enable A - When set, allows setting REQ A to cause an interrupt 
* INT ENB B - Interrupt Enable B
* CSR1 - Signal to user's hardware (on connector 1)
* CSR0 - Signal to user's hardware (on connector 2)

===Output Buffer Register (DROUTBUF)===
{{16bit-header}}
| colspan=16 | OUT15 <-> OUT0
{{16bit-bitout}}-->
== See also==

* [[DRV11 parallel interface]]

[[Category: QBUS Parallel Interfaces]]