View source for KD11-E/EA microcode

The engineering drawings for the [[KD11-E CPU]] and [[KD11-EA CPU]] provide nice [[flow chart]]s for the [[microcode]] in these [[Central Processing Unit|CPUs]]; with one tiny exception, the microcode in the two is identical. (The KD11-EA contains additional microcode associated with the [[FP11-A Floating-Point Processor]], which is not covered here.)

The difference is that the [[microinstruction]] 17-JJ is stored in location 002 in the KD11-E, and location 0744 in the KD11-EA. The reason for the change is unknown. Also, a dump of the KD11-EA microcode gives a different 'next microinstuction', from that given in the prints, for microinstruction 26-L (location 646); the prints show 9-F (location 320) as the next, but the dump gives 745. Again, the reason is unknown.

==Flow chart index==

The [[instruction]]s/functionality covered on each page are as follows:

{| class="wikitable"
! Page !! Contents
|-
| 2 || Instruction fetch and dispatch
|-
| 3 || Double op, source fetch
|-
| 4 || MOV
|-
| 5 || Double op, byte or SUB
|-
| 6 || Double op, destination fetch
|-
| 7 || Single op, modified dest
|-
| 8 || Single op, non-modified dest
|-
| 9 || JMP
|-
| 10 || JSR
|-
| 11 || SWAB
|-
| 12 || Shift, rotate
|-
| 13 || MFPI
|-
| 14 || MTPI
|-
| 15 || MTPS
|-
| 16 || MFPS
|-
| 17 || MARK, BR, RTS, CLx, SEx, SOB, RTI, RTT, NEG, WAIT, RESET
|-
| 18 || MUL/DIV
|-
| 19 || MUL
|-
| 20 || MUL
|-
| 21 || DIV
|-
| 22 || DIV
|-
| 23 || ASH/ASHC
|-
| 24 || Shift right
|-
| 25 || Shift left
|-
| 26 || Power on, trap
|}

==Microcode==

The following table, indexed by microinstruction number (in octal), gives the location of each microinstruction in the flow diagrams, the next microinstruction(s), and the operation performed by that microinstruction.

The microengine of the KD11-E/EA uses a technique called a 'branch microtest' (abbreviated to 'BUT' in the drawings), where the 'next microinstruction' field (in each microinstruction - there is no 'micro-PC') can be OR'd with various bits provided by the [[logic]] in the KD11-E/EA, to provide [[conditional branch]]ing. More than one bit at a time can be OR'd, thereby providing multi-way branching.

In the table below, for every microinstruction which can have variation as to the next microinstruction, all possible 'next microinstruction' destinations are listed. Note that depending on the bit(s) being tested, various bits of the 'next microinstruction' [[address]] may be set.

This can result in rather odd code layout, since a multi-way branch may require microinstructions to be scattered throughout the [[address space]], with a fixed numerical relationship among their addresses - the exact relationship depending on which bit is being tested.

One microinstruction (015), the main dispatch in instruction decoding, greatly extends the technique, with the aid of an instruction decode [[read-only memory|ROM]], so the next microinstruction in its case may be one of dozens. They are mostly arranged in groups of eight, with one of each group for each [[PDP-11 architecture#Addressing modes|addressing mode]] in the [[operand]]s. (In the table below, such a destination is notated as 'YYx'.)

During the transcription of this information, a number of errors in the drawings were found - places were two different microinstructions were assigned to the same location. These have been corrected (and checked against a dump of the microcode).

{| class="wikitable"
! μinstruction !! μcode flow diagram location !! next μinst !! Operation
|-
| 000 || 2-A || 016,017 || Service intr/trap, store vector
|-
| 001 || 26-M || 432 || Move PC to B
|-
| 002
|-
| 003 || 17-LL || 000 || Initialize system for 150msec
|-
| 004 || 17-L || 525 || Destination register to PC
|-
| 005 || 13-E || 371 || Fetch destination address, enable previous mode
|-
| 006 || 17-R || 541 || PSW to R12
|-
| 007 || 17-X || 542 || PSW to R12
|-
| colspan = "4" | &nbsp;
|-
| 010 || 14-D || 644 || Fetch word from top of stack
|-
| 011 || 17-EE || 645 || Fetch top of stack
|-
| 012 || 17-NN || 014 || No operation
|-
| 013 || 17-OO || 460 || Vector to R15
|-
| 014 || 17-MM || 012,013 || Service interrupt/trab, fetch vector
|-
| 015 || 2-C || + || Increment PC, ubranch on instruction
|-
| 016 || 2-B || 015 || Fetch next instruction, load into IR
|-
| 017 || 26-A || 460 || Move vector to R15
|-
| colspan = "4" | &nbsp;
|-
| 020 || 17-A || 553 || Sign extend BREG
|-
| 021 || 9-A || 000 || Jump address to PC
|-
| 022 || 9-C || 317 || Jump address to BREG
|-
| 023 || 9-D || 317 || Fetch jump address
|-
| 024 || 9-B || 021 || Decrement RDST, enable stack overflow
|-
| 025 || 9-G || 321 || Decrement RDST, enable stack overflow
|-
| 026 || 9-I || 322 || Fetch index data
|-
| 027 || 9-L || 324 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 030 || 11-A || 343 || Swap destination operand to R12
|-
| 031 || 11-C || 355 || Fetch swapped destination operand
|-
| 032 || 11-E || 344 || Fetch swapped destination operand
|-
| 033 || 11-G || 345 || Fetch destination address
|-
| 034 || 11-D || 031 || Decrement RDST, enable stack overflow
|-
| 035 || 11-I || 346 || Decrement RDST, enable stack overflow
|-
| 036 || 11-K || 347 || Fetch index data
|-
| 037 || 11-N || 351 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 040 || 7-A || 000 || Operate and load condition codes
|-
| 041 || 7-B || 217 || Fetch destination operand
|-
| 042 || 7-D || 275 || Fetch destination operand
|-
| 043 || 7-F || 276 || Fetch destination address
|-
| 044 || 7-C || 041 || Decrement RDST, enable stack overflow
|-
| 045 || 7-H || 277 || Decrement RDST, enable stack overflow
|-
| 046 || 7-K || 301 || Fetch index data
|-
| 047 || 7-M || 303 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 050 || 4-A || 000 || Operate and load condition codes
|-
| 051 || 4-B || 217 || Set up destination address
|-
| 052 || 4-P || 217 || Set up destination address, increment RDST
|-
| 053 || 4-F || 141 || Fetch destination address
|-
| 054 || 4-C || 051 || Decrement RDST, enable stack overflow
|-
| 055 || 4-H || 142 || Decrement RDST, enable stack overflow
|-
| 056 || 4-J || 144 || Fetch index data
|-
| 057 || 4-M || 146 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 060 || 6-A || 265 || Destination operand to BREG
|-
| 061 || 6-B || 265 || Fetch destination operand
|-
| 062 || 6-D || 263 || Fetch destination operand
|-
| 063 || 6-F || 264 || Fetch destination address
|-
| 064 || 6-C || 061 || Decrement RDST, enable stack overflow
|-
| 065 || 6-I || 266 || Decrement RDST, enable stack overflow
|-
| 066 || 6-L || 662 || Fetch index data
|-
| 067 || 6-O || 272 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 070 || 5-A || 050 || Destination operand to BREG
|-
| 071 || 5-B || 217 || Fetch destination operand
|-
| 072 || 5-D || 242 || Fetch destination operand
|-
| 073 || 5-F || 243 || Fetch destination address
|-
| 074 || 5-C || 071 || Decrement RDST, enable stack overflow
|-
| 075 || 5-H || 244 || Decrement RDST, enable stack overflow
|-
| 076 || 5-K || 246 || Fetch index data
|-
| 077 || 5-N || 661 || Fetch index data
|-
| colspan="4" | &nbsp;&nbsp;
|-
| 100 || 13-A || 463 || Destination data to R12, enable previous mode
|-
| 101 || 13-B || 455 || Move destination address to R12
|-
| 102 || 13-D || 005 || Move destination address to R12
|-
| 103 || 13-G || 372 || Fetch destination address
|-
| 104 || 13-C || 101 || Decrement RDST, enable stack overflow
|-
| 105 || 13-I || 373 || Decrement RDST, enable stack overflow
|-
| 106 || 13-K || 374 || Fetch index data
|-
| 107 || 13-N || 376 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 110 || 3-A || 05x, 06x. 07x || Source operand to R12 and BREG
|-
| 111 || 3-B || 05x, 06x. 07x || Fetch source operand
|-
| 112 || 3-D || 205 || Fetch source operand
|-
| 113 || 3-F || 206 || Fetch source address
|-
| 114 || 3-C || 111 || Decrement RSRC, enable stack overflow
|-
| 115 || 3-H || 207 || Decrement RSRC, enable stack overflow
|-
| 116 || 3-K || 212 || Fetch index data
|-
| 117 || 3-N || 214 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 120 || 15-A || 675 || Destination operand to R12 and BREG
|-
| 121 || 15-F || 675 || Fetch destination operand
|-
| 122 || 15-H || 663 || Fetch destination operand
|-
| 123 || 15-J || 664 || Fetch destination address
|-
| 124 || 15-G || 121 || Decrement RDST, enable stack overflow
|-
| 125 || 15-M || 665 || Decrement RDST, enable stack overflow
|-
| 126 || 15-O || 667 || Fetch index data
|-
| 127 || 15-R || 672 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 130 || 16-A || 705 || PSW data to R12
|-
| 131 || 16-C || 706 || Place destination address on bus address lines
|-
| 132 || 16-F || 706 || Destination address to bus, increment RDST
|-
| 133 || 16-G || 710 || Fetch destination address
|-
| 134 || 16-E || 131 || Decrement RDST, enable stack overflow
|-
| 135 || 16-J || 711 || Decrement RDST, enable stack overflow
|-
| 136 || 16-L || 712 || Fetch index data
|-
| 137 || 16-O || 714 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 140 || 17-U || 210 || RDST to BREG
|-
| 141 || 4-G || 143 || Increment RDST
|-
| 142 || 4-I || 143 || Fetch destination address
|-
| 143 || 4-Q || 217 || Setup destination address, enable KT maintenance
|-
| 144 || 4-K || 145 || Increment PC
|-
| 145 || 4-L || 143 || Determine destination address
|-
| 146 || 4-N || 147 || Increment PC
|-
| 147 || 4-O || 241 || Determine address of destination address
|-
| colspan = "4" | &nbsp;
|-
| 150 || 17-KK || 07x || Zero R12
|-
| 151 || 10-A || 336 || Jump address to BREG
|-
| 152 || 10-C || 327 || Jump address to BREG
|-
| 153 || 10-D || 327 || Fetch jump address
|-
| 154 || 10-B || 336 || Decrement RDST, jump address to BREG
|-
| 155 || 10-F || 330 || Decrement RDST, enable stack overflow
|-
| 156 || 10-H || 331 || Fetch index data
|-
| 157 || 10-K || 333 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 160 || 8-A || 000 || Operate on operand, load condition codes
|-
| 161 || 8-B || 265 || Fetch destination operand
|-
| 162 || 8-D || 306 || Fetch destination operand
|-
| 163 || 8-F || 307 || Fetch destination address
|-
| 164 || 8-C || 161 || Decrement RDST, enable stack overflow
|-
| 165 || 8-H || 310 || Decrement RDST, enable stack overflow
|-
| 166 || 8-K || 312 || Fetch index data
|-
| 167 || 8-N || 314 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 170 || 12-A || 356 || Destination operand to BREG
|-
| 171 || 12-C || 370 || Fetch destination operand
|-
| 172 || 12-E || 357 || Fetch destination operand
|-
| 173 || 12-G || 360 || Fetch destination addressa
|-
| 174 || 12-D || 171 || Decrement RDST, enable stack overflow
|-
| 175 || 12-I || 361 || Decrement RDST, enable stack overflow
|-
| 176 || 12-L || 363 || Fetch index data
|-
| 177 || 12-O || 365 || Fetch index data
|-
| colspan = "4" | &nbsp;&nbsp;
|-
| 200 || 17-I || 522 || Sign extend BREG
|-
| 201 || 26-FF || 202 || Set R15 to 26
|-
| 202 || 26-GG || 577 || Fetch new PSW
|-
| 203 || 17-Q || 000 || Operate, set condition codes
|-
| 204 || 17-W || 000 || Operate, set condition codes
|-
| 205 || 3-E || 05x,06x,07x || Increment RSRC
|-
| 206 || 3-G || 211 || Increment RSRC
|-
| 207 || 3-I || 211 || Fetch source address
|-
| colspan = "4" | &nbsp;
|-
| 210 || 17-T || 000 || Operate, send condition codes
|-
| 211 || 3-J || 05x,06x,07x || Fetch source operand
|-
| 212 || 3-L || 213 || Increment PC
|-
| 213 || 3-M || 211 || Determine source address
|-
| 214 || 3-O || 215 || Increment PC
|-
| 215 || 3-P || 216 || Determine address of source address
|-
| 216 || 3-Q || 211 || Fetch source address
|-
| 217 || 4-E || 000 || Get destination data and store, enable KT maintenance
|-
| colspan = "4" | &nbsp;
|-
| 220 || 18-A || 602 || Fetch multiplicand/divisor
|-
| 221 || 18-B || 602 || Fetch multiplicand/divisor
|-
| 222 || 18-D || 563 || Fetch multiplicand/divisor
|-
| 223 || 18-F || 565 || Fetch destination address
|-
| 224 || 18-C || 221 || Decrement RDST, enable stack overflow
|-
| 225 || 18-H || 567 || Decrement RDST, enable stack overflow
|-
| 226 || 18-J || 571 || Fetch index data
|-
| 227 || 18-M || 575 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 230 || 23-A || 633 || Fetch shift count
|-
| 231 || 23-B || 633 || Fetch shift count
|-
| 232 || 23-D || 621 || Fetch shift count
|-
| 233 || 23-F || 622 || Fetch destination address
|-
| 234 || 23-C || 231 || Decrement RDST, enable stack overflow
|-
| 235 || 23-H || 624 || Decrement RDST, enable stack overflow
|-
| 236 || 23-J || 625 || Fetch index data
|-
| 237 || 23-M || 627 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 240 || 17-V || 204 || RSRC to BREG
|-
| 241 || 4-P || 143 || Fetch destination address
|-
| 242 || 5-E || 217 || Increment RDST
|-
| 243 || 5-G || 245 || Increment RDST
|-
| 244 || 5-I || 245 || Fetch destination address
|-
| 245 || 5-J || 217 || Fetch destination operand
|-
| 246 || 5-L || 247 || Increment PC
|-
| 247 || 5-M || 245 || Determine destination address
|-
| colspan = "4" | &nbsp;
|-
| 250 || 14-A || 000 || Move data to desination register
|-
| 251 || 14-B || 513 || Move destination address to R13
|-
| 252 || 14-F || 474 || Move destination address to R13
|-
| 253 || 14-H || 474 || Fetch destination address
|-
| 254 || 14-C || 251 || Decrement RDST, enable stack overflow
|-
| 255 || 14-I || 475 || Decrement RDST, enable stack overflow
|-
| 256 || 14-K || 476 || Fetch index data
|-
| 257 || 14-N || 506 || Fetch index data
|-
| colspan = "4" | &nbsp;
|-
| 260 || 17-Z || 700,702 || Decrement RSRC, branch on 0
|-
| 261 || 5-P || 262 || Determine address of destination address
|-
| 262 || 5-Q || 245 || Fetch destination address
|-
| 263 || 6-E || 265 || Increment RDST
|-
| 264 || 6-G || 267 || Increment RDST
|-
| 265 || 6-H || 000 || Operate and load condition codes
|-
| 266 || 6-J || 267 || Fetch destination address
|-
| 267 || 6-K || 265 || Fetch destination operand
|-
| colspan = "4" | &nbsp;
|-
| 270 || 17-P || 203 || RDEST to BREG
|-
| 271 || 6-N || 267 || Determine destination address
|-
| 272 || 6-P || 273 || Increment PC
|-
| 273 || 6-Q || 274 || Determine address of destination address
|-
| 274 || 6-R || 267 || Fetch destination address
|-
| 275 || 7-E || 217 || Increment RDST
|-
| 276 || 7-G || 300 || Increment RDST
|-
| 277 || 7-I || 300 || Fetch destination address
|-
| colspan = "4" | &nbsp;&nbsp;
|-
| 300 || 7-J || 217 || Fetch destination operand
|-
| 301 || 7-L || 302 || Increment PC
|-
| 302 || 7-M || 300 || Determine destination address
|-
| 303 || 7-O || 304 || Increment PC
|-
| 304 || 7-P || 305 || Determine address of destination address
|-
| 305 || 7-Q || 300 || Fetch destination address
|-
| 306 || 8-E || 265 || Increment RDST
|-
| 307 || 8-G || 311 || Increment RDST
|-
| colspan = "4" | &nbsp;
|-
| 310 || 8-I || 311 || Fetch destination address
|-
| 311 || 8-J || 265 || Fetch destination operand
|-
| 312 || 8-L || 313 || Increment PC
|-
| 313 || 8-M || 311 || Determine desination address
|-
| 314 || 8-O || 315 || Increment PC
|-
| 315 || 8-P || 316 || Determine address of desination address
|-
| 316 || 8-Q || 311 || Fetch destination address
|-
| 317 || 9-E || 320 || Increment RDST
|-
| colspan = "4" | &nbsp;
|-
| 320 || 9-F || 000 || Jump address to PC
|-
| 321 || 9-H || 320 || Fetch jump address
|-
| 322 || 9-J || 323 || Increment PC
|-
| 323 || 9-K || 000 || Determine jump address
|-
| 324 || 9-M || 325 || Increment PC
|-
| 325 || 9-N || 326 || Determine address of jump address
|-
| 326 || 9-O || 320 || Fetch jump address
|-
| 327 || 10-E || 336 || Increment RDST
|-
| colspan = "4" | &nbsp;
|-
| 330 || 10-G || 336 || Fetch jump address
|-
| 331 || 10-I || 332 || Increment PC
|-
| 332 || 10-J || 336 || Determine jump address
|-
| 333 || 10-L || 334 || Increment PC
|-
| 334 || 10-M || 335 || Determine address of jump address
|-
| 335 || 10-N || 336 || Fetch jump address
|-
| 336 || 10-O || 337 || Decrement SP
|-
| 337 || 10-P || 340 || Set up bus address
|-
| colspan = "4" | &nbsp;
|-
| 340<sup>1</sup> || 10-Q || 341 || Output RSRC to stack
|-
| 341 || 10-R || 342 || Move PC to RSRC
|-
| 342 || 10-S || 000 || BREG to PC
|-
| 343 || 11-B || 000 || Load condition codes
|-
| 344 || 11-F || 355 || Increment RDST
|-
| 345 || 11-H || 354 || Increment RDST
|-
| 346 || 11-J || 354 || Fetch destination address
|-
| 347 || 11-L || 350 || Increment PC
|-
| colspan = "4" | &nbsp;
|-
| 350 || 11-M || 354 || Determine destination address
|-
| 351 || 11-O || 352 || Increment PC
|-
| 352 || 11-P || 353 || Determine address of destination address
|-
| 353 || 11-Q || 354 || Fetch destination address
|-
| 354 || 11-R || 355 || Fetch swapped destination operand
|-
| 355 || 11-S || 000 || Store data, load condition codes
|-
| 356 || 12-B || 050 || Shift operand
|-
| 357<sup>2</sup> || 12-F || 370 || Increment RDST
|-
| colspan = "4" | &nbsp;
|-
| 360 || 12-H || 362 || Increment RDST
|-
| 361 || 12-J || 362 || Fetch destination address
|-
| 362 || 12-K || 370 || Fetch destination operand
|-
| 363 || 12-M || 364 || Increment PC
|-
| 364 || 12-N || 362 || Determine destination address
|-
| 365 || 12-P || 366 || Increment PC
|-
| 366 || 12-Q || 367 || Determine address of destination address
|-
| 367 || 12-R || 362 || Fetch destination address
|-
| colspan = "4" | &nbsp;
|-
| 370 || 12-S || 217 || Shift operand
|-
| 371 || 13-F || 463 || Increment RDST
|-
| 372 || 13-H || 455 || Increment RDST
|-
| 373 || 13-J || 455 || Fetch destination address
|-
| 374 || 13-L || 375 || Increment PC
|-
| 375 || 13-M || 455 || Determine destination address
|-
| 376 || 13-O || 377 || Increment PC
|-
| 377 || 13-P || 643 || Determine address of destination address
|-
| colspan = "4" | &nbsp;&nbsp;
|-
| 400 || 18-S || 402,502 || Complement & test sign of multiplicand
|-
| 401 || 18-T || 404,406 || Test divisor for zero
|-
| 402 || 19-A || 403,503 || Zero R17 and B, test multiplicand
|-
| 403 || 19-J || 606 || Put multiplier in BX
|-
| 404 || 21-A || 612 || Put one's complement of divisor in R13
|-
| 405 || 19-D || 407 || Put one's complement of multiplier in R13
|-
| 406 || 22-W || 620 || Set V bit
|-
| 407 || 19-U || 413,417,433,437,<br>453,457,473,477 || Shift right (partial product, multiplier), decrement counter
|-
| colspan = "4" | &nbsp;
|-
| 410 || 20-C || 420,422 || Test upper product for all 1's
|-
| 411 || 20-L || 611 || Clear C bit
|-
| 412 || 20-H || 414,416|| Test lower product for zero
|-
| 413 || 19-M || 413,417,433,437,<br>453,457,473,477 || Shift right (partial product, multiplier), decrement counter
|-
| 414 || 20-J || 411,511 || Test MSB of lower product
|-
| 415 || 20-G || 611 || Set C bit
|-
| 416 || 20-I || 414 || Set Z bit
|-
| 417 || 19-P || 607 || Store upper product
|-
| colspan = "4" | &nbsp;
|-
| 420 || 20-E || 415 || Set V bit
|-
| 421 || 21-L || 424 || Fetch lower dividend
|-
| 422 || 20-D || 415,515 || Test MSB of lower product
|-
| 423 || 21-F || 424 || Take one's complement of upper dividend
|-
| 424 || 21-M || 425,435 || Shift upper dividend left, test sign of divisor
|-
| 425 || 21-O || 440,442 || Subtract divisor from dividend, test remainder
|-
| 426 || 22-S || 616 || Set V bit
|-
| 427 || 19-L || 407 || Subtract multiplicand from partial product
|-
| colspan = "4" | &nbsp;
|-
| 430 || 25-A || 452,456 || Test counter for 0, fetch upper part of operand
|-
| 431 || 22-J || 616 || Clear V bit
|-
| 432 || 26-N || 731 || Move PC to R5
|-
| 433 || 19-T || 473 || Add multiplicand to partial product
|-
| 434 || 24-A || 516,517 || Test IR9 to determine ASH/ASHC
|-
| 435 || 21-N || 440,442 || Subtract divisor from dividend, test remainder
|-
| 436 || 17-D || 556 || BREG to SP
|-
| 437 || 19-Q || 607 || Store upper product
|-
| colspan = "4" | &nbsp;
|-
| 440 || 21-P || 442,462 || Test first quotient bit
|-
| 441 || 22-B || 461 || Add divisor to remainder
|-
| 442 || 21-G || 640,650,660,670 || Shift remainder left, test sign of divisor, test LSB of quotient
|-
| 443 || 22-N || 615 || Srore remainder
|-
| 444 || 22-D || 614 || Srore remainder
|-
| 445 || 24-E || 635 || Save BX in B, clear N bit
|-
| 446 || 22-A || 441,451,461,471 || Test quotient LSB and sign of divisor
|-
| 447 || 24-D || 634 || Save BX in B, clear N bit
|-
| colspan = "4" | &nbsp;
|-
| 450<sup>3</sup> || 17-II || 744 || Step SP
|-
| 451 || 22-K || 471 || Add divisor to remainder
|-
| 452 || 25-D || 652,653 || Test IR9 to determine ASH/ASHC, fetch lower part of operand
|-
| 453 || 19-O || 413 || Subtract multiplicand from partial product
|-
| 454 || 24-K || 641 || Clear C bit
|-
| 455 || 13-R || 463 || Fetch destination data, enable previous mode
|-
| 456 || 25-B || 500,501 || Test IR9 to determine ASH/ASHC
|-
| 457 || 19-R || 607 || Store upper product
|-
| colspan = "4" | &nbsp;
|-
| 460 || 26-B || 470 || Move PSW to B
|-
| 461 || 22-C || 444,544 || Test sign of dividend
|-
| 462 || 22-Y || 000 || Set V bit
|-
| 463 || 13-S || 472 || Decrement SP
|-
| 464 || 24-U || 465 || Store lower result, clear N bit
|-
| 465 || 24-X || 637 || Clear Z bit
|-
| 466 || 24-T || 465,467 || Store lower result, clear N bit, test for 0
|-
| 467 || 24-W || 637 || Clear Z bit
|-
| colspan = "4" | &nbsp;
|-
| 470 || 26-C || 504 || Increment vector address
|-
| 471 || 22-L || 443,543 || Test sign of dividend
|-
| 472 || 13-P || 217 || Set up bus address
|-
| 473 || 19-N || 413,417,433,437,<br>453,457,473,477 || Shift right (partial product, multiplier), decrement counter
|-
| 474 || 14-G || 513 || Increment RDST
|-
| 475 || 14-J || 513 || Fetch destination address
|-
| 476 || 14-L || 552 || Increment PC
|-
| 477 || 19-S || 607 || Store upper product
|-
| colspan = "4" | &nbsp;&nbsp;
|-
| 500 || 25-C || 512 || Clear BX to indicate C bit = 0
|-
| 501 || 25-M || 651 || No operation
|-
| 502 || 19-I || 403 || Zero R17 and B
|-
| 503 || 19-B || 405,505 || Put multiplier in R12 and test sign
|-
| 504 || 26-D || 560 || Fetch new PSW
|-
| 505 || 19-C || 603 || Put one's complement of multiplier in R13
|-
| 506 || 14-D || 510 || Increment PC
|-
| 507 || 19-F || 604 || Shift right (100000, 100000)
|-
| colspan = "4" | &nbsp;
|-
| 510 || 14-P || 514 || Determine address of destination address
|-
| 511 || 20-K || 611 || Set C bit
|-
| 512 || 24-C || 445,447,545 || Store upper result, test sign of Z bit
|-
| 513 || 14-R || 520 || Setup bus address, enable previous mode
|-
| 514 || 14-Q || 513 || Fetch destination address
|-
| 515 || 20-F || 611 || Clear C bit
|-
| 516 || 24-B || 512,516 || Shift upper part of operand
|-
| 517 || 24-O || 707 || Fetch lower part of operand
|-
| colspan = "4" | &nbsp;
|-
| 520 || 14-S || 000 || Output data to destination address
|-
| 521 || 21-C || 613 || Fetch lower dividend
|-
| 522 || 17-J || 523 || Shift BREG left one bit
|-
| 523 || 17-K || 000 || Add offset to PC
|-
| 524 || 22-V || 000 || Set V bit
|-
| 525 || 17-M || 527 || Fetch top of stack
|-
| 526 || 22-R || 616 || Clear V bit
|-
| 527 || 17-N || 533 || Step stack to pointer
|-
| colspan = "4" | &nbsp;
|-
| 530 || 22-G || 431,531 || Clear U bit
|-
| 531 || 22-I || 616 || Set V bit
|-
| 532 || 22-H || 431 || Clear N bit, set Z bit
|-
| 533 || 17-O || 000 || Load stack data into destination register
|-
| 534 || 22-Q || 426,526 || Clear V bit
|-
| 535 || 17-GG || 537 || Step SP
|-
| 536 || 22-P || 526 || Clear N bit, set Z bit
|-
| 537 || 17-HH || 450 || Fetch top of stack
|-
| colspan = "4" | &nbsp;
|-
| 540 || 26-KK || 741 || Clear IR to halt processor
|-
| 541 || 17-S || 000 || Mask and set condition codes
|-
| 542 || 17-Y || 000 || Mask and set condition codes
|-
| 543 || 22-M || 614 || Srore remainder
|-
| 544 || 22-E || 615 || Srore remainder
|-
| 545 || 24-F || 635 || Save BX in B, set N bit
|-
| 546 || 17-CC || 547 || Calculate offset
|-
| 547 || 17-DD || 000 || Subtract offset from PC
|-
| colspan = "4" | &nbsp;
|-
| 550 || 24-M || 641 || Clear C bit
|-
| 551 || 17-G || 561 || Data to R5
|-
| 552 || 14-M || 513 || Determine destination address
|-
| 553 || 17-B || 555 || Shift BREG left, R5 to BXREG
|-
| 554 || 24-L || 641 || Set C bit
|-
| 555 || 17-C || 436 || Add PC to BREG
|-
| 556 || 17-E || 557 || BXREG to PC
|-
| 557 || 17-F || 551 || Fetch top of stack
|-
| colspan = "4" | &nbsp;
|-
| 560 || 26-E || 562 || R6 <- R6-2, enable stack overflow
|-
| 561 || 17-H || 000 || Step SP
|-
| 562 || 26-F || 566 || Place SP address on bus lines
|-
| 563 || 18-E || 602 || Increment RDST
|-
| 564 || 24-V || 465 || Store lower result, set N bit
|-
| 565 || 18-G || 601 || Increment RDST
|-
| 566 || 26-G || 570 || Output old PSW, enable double bus errors
|-
| 567 || 18-I || 601 || Fetch destination address
|-
| colspan = "4" | &nbsp;
|-
| 570 || 26-H || 572 || Decrement SP, enable stack overflow
|-
| 571 || 18-K || 574 || Increment PC
|-
| 572 || 26-I || 573 || Place SP address on bus lines
|-
| 573 || 26-J || 577 || Push old PC on stack
|-
| 574 || 18-L || 601 || Determine destination address
|-
| 575 || 18-N || 576 || Increment PC
|-
| 576 || 18-O || 600 || Determine address of destination address
|-
| 577 || 26-K || 646 || Decrement vector address
|-
| colspan = "4" | &nbsp;&nbsp;
|-
| 600 || 18-P || 601 || Fetch destination address
|-
| 601 || 18-Q || 602 || Fetch multiplicand/divisor
|-
| 602 || 18-R || 400,401 || Load step counter, test IR9 for multiply/divide
|-
| 603 || 19-E || 407,507 || Test two's complement of multiplier
|-
| 604 || 19-G || 605 || Load B and R5 with 040000
|-
| 605 || 19-H || 610 || Zero lower product
|-
| 606 || 19-K || 407,427 || Test LSB of BX for first multiply step
|-
| 607 || 20-A || 610 || Store lower product
|-
| colspan = "4" | &nbsp;
|-
| 610 || 20-B || 701 || C out is the sign of the product
|-
| 611 || 20-M || 000 || Transfer condition codes to PSW
|-
| 612 || 21-B || 421,521 || Fetch upper dividend and test sign
|-
| 613 || 21-D || 423,623 || Take two's complement of lower dividend
|-
| 614 || 22-F || 530,532 || Store quotient, clear N bit
|-
| 615 || 22-O || 534,536 || Store quotient, set N bit
|-
| 616 || 22-T || 617 || Clear C bit
|-
| 617 || 22-U || 000 || Transfer condition codes to PSW
|-
| colspan = "4" | &nbsp;
|-
| 620 || 22-X || 000 || Set C bit
|-
| 621 || 23-E || 633 || Increment RDST
|-
| 622 || 23-G || 632 || Increment RDST
|-
| 623 || 21-E || 424,524 || Take two's complement of upper dividend
|-
| 624 || 23-I || 632 || Fetch destination address
|-
| 625 || 23-K || 626 || Increment PC
|-
| 626 || 23-L || 632 || Determine destination address
|-
| 627 || 23-N || 630 || Increment PC
|-
| colspan = "4" | &nbsp;
|-
| 630 || 23-O || 631 || Determine address of destination address
|-
| 631 || 23-P || 632 || Fetch destination address
|-
| 632 || 23-Q || 633 || Fetch shift count
|-
| 633 || 23-R || 430,434 || Test sign of counter
|-
| 634 || 24-G || 636 || Set Z bit
|-
| 635 || 24-H || 636 || Clear Z bit
|-
| 636 || 24-I || 454,554 || V bit <- OVX
|-
| 637 || 24-J || 550,554 || V bit <- OVX
|-
| colspan = "4" | &nbsp;
|-
| 640 || 21-J || 442,446 || Add divisor to remainder, test counter sign
|-
| 641 || 24-N || 000 || Transfer condition codes to PSW
|-
| 642 || 14-E || 25x || Increment SP
|-
| 643 || 13-Q || 455 || Fetch destination address
|-
| 644 || 14-T || 642 || Move stack data to R12
|-
| 645 || 17-FF || 535 || Data to PC
|-
| 646<sup>4</sup> || 26-L || 320 || Fetch new PC
|-
| 647 || 26-CC || 654 || Add 2 to R15
|-
| colspan = "4" | &nbsp;
|-
| 650 || 21-K || 442,446 || Add divisor to remainder, test counter sign
|-
| 651 || 25-N || 464,466,564 || Store upper result, test sign of Z bit
|-
| 652 || 25-H || 753 || Clear BX so that 0's shift into B
|-
| 653 || 25-E || 653,657 || Shift double operand left, decrement counter
|-
| 654 || 26-DD || 656 || Set R15 to 5
|-
| 655 || 25-K || 512 || Clear BX to indicate C bit is 0
|-
| 656 || 26-EE || 201 || Set R15 to 013
|-
| 657 || 25-F || 651,751 || Test R17 to determine C bit
|-
| colspan = "4" | &nbsp;
|-
| 660 || 21-H || 442,446 || Subtract divisor from remainder, test counter sign
|-
| 661 || 5-O || 261 || Increment PC
|-
| 662 || 6-M || 271 || Increment PC
|-
| 663 || 15-I || 675 || Increment RDST
|-
| 664 || 15-K || 666 || Increment RDST
|-
| 665 || 15-N || 666 || Fetch destination address
|-
| 666 || 15-L || 675 || Fetch destination operand
|-
| 667 || 15-P || 671 || Increment PC
|-
| colspan = "4" | &nbsp;
|-
| 670 || 21-I || 442,446 || Subtract divisor from remainder, test counter sign
|-
| 671 || 15-Q || 666 || Determine destination address
|-
| 672 || 15-S || 673 || Increment PC
|-
| 673 || 15-T || 674 || Determine address of destination address
|-
| 674 || 15-U || 666 || Fetch destination address
|-
| 675 || 15-B || 676 || Set R17 to all 1's
|-
| 676 || 15-C || 677 || Set R17 equal to PSW address
|-
| 677 || 15-D || 704 || Place PSW address on bus address lines
|-
| colspan = "4" | &nbsp;&nbsp;
|-
| 700 || 17-BB || 546 || Swap bytes, shift BREG left
|-
| 701 || 20-N || 410,412 || Test upper product for zero
|-
| 702 || 17-AA || 000 || No operation
|-
| 703 || 24-R || 723 || Clear counter to indicate C bit is 0
|-
| 704 || 15-E || 000 || Output destination operand to PSW
|-
| 705 || 16-B || 000 || Move R12 to RDST
|-
| 706 || 16-D || 217 || Move PSW data to R12
|-
| 707 || 24-Q || 703,707,723,727 || Shift double operand right, increment counter
|-
| colspan = "4" | &nbsp;
|-
| 710 || 16-H || 717 || Increment RDST
|-
| 711 || 16-K || 717 || Fetch destination address
|-
| 712 || 16-M || 713 || Increment PC
|-
| 713 || 16-N || 717 || Determine destination address
|-
| 714 || 16-P || 715 || Increment PC
|-
| 715 || 16-Q || 716 || Determine address of destination address
|-
| 716 || 16-R || 717 || Fetch destination address
|-
| 717 || 16-I || 706 || Place destination address on bus address lines
|-
| colspan = "4" | &nbsp;
|-
| 720 || 26-HH || 741 || Clear IR to halt processor
|-
| 721 || 26-Z || 737 || Shift B left, zero B LSB
|-
| 722 || 26-Q || 734 || Put all 1's in the PC
|-
| 723 || 24-S || 464,466,564 || Store upper result, test sign of Z bit
|-
| 724 || 26-S || 735 || Move all 1's to B
|-
| 725 || 26-AA || 540,740 || Increment PC, branch on COUT
|-
| 726 || 26-II || 741 || Clear IR to halt processor
|-
| 727 || 24-P || 703,707,723,727 || Shift double operand right, increment counter
|-
| colspan = "4" | &nbsp;
|-
| 730 || 26-JJ || 741 || Clear IR to halt processor
|-
| 731 || 26-O || 733 || Clear PC
|-
| 732 || 26-U || 736 || Move 016 to counter
|-
| 733 || 26-P || 720,722 || Test for 0 PC
|-
| 734 || 26-R || 724,726 || Test for 0 PC
|-
| 735 || 26-T || 730,732 || XOR PC and B
|-
| 736 || 26-V || 743 || Clear B
|-
| 737 || 26-X || 742 || Move B to BX
|-
| colspan = "4" | &nbsp;
|-
| 740 || 26-BB || 647 || Clear R15
|-
| 741 || 26-LL || 000 || No operation
|-
| 742 || 26-Y || 721,725 || Add PC and BX, decrement count
|-
| 743 || 26-W || 737 || Put 1 in B
|-
| 744 || 17-JJ || 000 || Data to PSW
|-
| 745
|-
| 746
|-
| 747
|-
| colspan = "4" | &nbsp;
|-
| 750
|-
| 751 || 25-G || 651 || Set counter to indicate C bit is 1
|-
| 752
|-
| 753 || 25-I || 753,757 || Shift single operand left, decrement counter
|-
| 754
|-
| 755 || 25-L || 512 || Set BX to indicate C bit is 1
|-
| 756
|-
| 757 || 25-J || 655,755 || Test R17 to determine C bit
<!-- |-
| colspan = "4" | &nbsp;
|-
| 760
|-
| 761
|-
| 762
|-
| 763
|-
| 764
|-
| 765
|-
| 766
|-
| 767
|-
| colspan = "4" | &nbsp;
|-
| 770
|-
| 771
|-
| 772
|-
| 773
|-
| 774
|-
| 775
|-
| 776
|-
| 777 -->
|}

Notes:

1 - prints say 346; '6' written for '0'
<br>
2 - prints say 375; digit swap
<br>
3 - prints say 540; digit swap
<br>
4 - prints give a different 'next' from a microcode dump

+ - This is the main instruction decode multi-way branch. Possible next microinstructions include:

* 11x (indirect to 05x, 07x, 06x)
* 04x, 16x, 02x, 15x, 03x, 17x, 10x, 25x, 12x, 13x, 22x, 23x (instructions)
* 003, 004, 006, 007, 011, 014, 020, 150, 200, 260 (individual instructions)
* 270, 210, 240, 140 (simple instructions)

==External links==

* [http://www.bitsavers.org/pdf/dec/pdp11/1134/MP00082_1134_Vol2_Sep76.pdf 11/34 Vol 2. Field Maintenance Print Set] (MP00082) - contains microcode Flow Diagrams (on pp. 15-40 of the PDF)
* [http://www.bitsavers.org/pdf/dec/pdp11/1134/m8266_ucode.out.txt Dump of KD11-EA microcode on BitSavers] (in symbolic form)

[[Category: PDP-11 UNIBUS Processors]]