Difference between revisions of "MOS Technology 6502"

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===Introduction===
 
===Introduction===
−
The MOS Technology 6502 is an 8-bit microprocessor that was designed by Chuck Peddle for [[MOS Technology]] in 1975. When it was introduced, it was the least expensive full-featured CPU on the market by a considerable margin, costing less than one-sixth the price of competing designs from larger companies such as Motorola and Intel. It was nevertheless faster than most of them, and, along with the [[Zilog Z80]], sparked a series of computer projects that would eventually result in the home computer revolution of the 1980s.  
+
The MOS Technology 6502 is an 8-bit microprocessor that was designed by Chuck Peddle and Bill Mensch for [[MOS Technology]] in 1975. When it was introduced at around $25 it was the least expensive full-featured CPU on the market by a considerable margin, costing less than one-sixth the price of competing designs from larger companies such as Motorola and Intel. It was nevertheless faster than most of them, and, along with the [[Zilog Z80]], sparked a series of computer projects that would eventually result in the home computer revolution of the 1980s.  
  
 
It was widely used in [[Apple]], [[Atari]] and [[BBC]] computers, plus of course [[Commodore]], the company which eventually bought out MOS Technology.
 
It was widely used in [[Apple]], [[Atari]] and [[BBC]] computers, plus of course [[Commodore]], the company which eventually bought out MOS Technology.
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[[Image:MOS 6502AD 4585 top.jpg]]
 
[[Image:MOS 6502AD 4585 top.jpg]]
  
−
The original [[NMOS]] 6502 turned out to have unusually few bugs during the development cycle, unlike some competitors, but there were still a small number of quirks that occasionally created trouble. The most well-known one was probably the 'JMP ($xxFF)' bug. This is a jump to an indirect address, where the LSB of the destination address is in location $xxFF ('xx' can be whatever), and the MSB of the destination address is in location $xy00, where xy = xx+1. The bug is that in the case where the LSB byte is in the last address of a page (as indicated by the FF) the MSB is not read from the first byte of the next page but instead it's read from the first byte of the current page. So, if we have JMP ($05FF) the address should be composed of an LSB from $05FF and an MSB from $0600. Instead the MSB is read from $0500. This bug would be rare enough that a user may never be hit by it, particularly when using an assembler which knew about the bug and could detect a problematic address.
+
The original [[NMOS]] 6502 turned out to have unusually few bugs during the development cycle, unlike some competitors, but there were still a small number of quirks that occasionally created trouble. An early bug was the malfunctioning 'ROR' instruction on pre-June 1976 CPUs. The instruction basically behaved like 'ASL' (Arithmetic Shift Left). Due to this problem the ROR instruction was only documented as "''will be available on MCS650X microprocessors after June, 1976''". Very early computers like the [[KIM-1]] produced in 1975 were fitted with 6502 CPUs with the ROR bug.
 +
 
 +
A more longer lasting issue (affecting all NMOS 6502 CPUs) was the 'JMP ($xxFF)' bug. This is a jump to an indirect address, where the LSB of the destination address is in location $xxFF ('xx' can be whatever), and the MSB of the destination address is in location $xy00, where xy = xx+1. The bug is that in the case where the LSB byte is in the last address of a page (as indicated by the FF) the MSB is not read from the first byte of the next page but instead it's read from the first byte of the current page. So, if we have JMP ($05FF) the address should be composed of an LSB from $05FF and an MSB from $0600. Instead the MSB is read from $0500. This bug would be rare enough that a user may never be hit by it, particularly when using an assembler which knew about the bug and could detect a problematic address.
  
 
===The CMOS version===
 
===The CMOS version===
−
This bug, and a couple of others, were removed when the processor was redesigned using [[CMOS]] instead of NMOS. The CMOS version was designed by Bill Mensch (one of the original designers of the [[MC6800 | 6800]] and the NMOS 6502). It was licensed to many different companies for production, where some of them would use slightly different designs to fit their specific needs. The most well-known versions are the Rockwell 65C02 and Western Design Center (WDC) 65C02. Other variants were made by [[Synertek]][1] and [[General Telephone and Electric | GTE]] (the GTE version worked well as a drop-in replacement for the NMOS 6502 even in older Apple II computers, although later Apple would use Rockwell 65C02 chips in the Apple IIe and IIc models). WDC continued to design other variants of the 65C02 and are still at it as of 2014. There were other manufacturers as well, including but not limited to [[National Cash Register| NCR]], [[California Micro Devices]], and Ricoh. Ricoh made a variant for the Nintendo game system, this version missed the BCD instructions - presumably never needed for Nintendo games.
+
The JMP bug, and a couple of others, were removed when the processor was redesigned using [[CMOS]] instead of NMOS. The CMOS version was designed by Bill Mensch (one of the original designers of the [[MC6800 | 6800]] and the NMOS 6502). It was licensed to many different companies for production, where some of them would use slightly different designs to fit their specific needs. The most well-known versions are the Rockwell 65C02 and Western Design Center (WDC) 65C02. Other variants were made by [[Synertek]][1] and [[General Telephone and Electric | GTE]] (the GTE version worked well as a drop-in replacement for the NMOS 6502 even in older Apple II computers, although later Apple would use Rockwell 65C02 chips in the Apple IIe and IIc models). WDC continued to design other variants of the 65C02 and are still at it as of 2014. There were other manufacturers as well, including but not limited to [[National Cash Register| NCR]], [[California Micro Devices]], and Ricoh. Ricoh made a variant for the Nintendo game system, this version missed the BCD instructions - presumably never needed for Nintendo games.
  
 
[1]Synertek and Rockwell were also second-source vendors of the NMOS 6502
 
[1]Synertek and Rockwell were also second-source vendors of the NMOS 6502
  
 
===Other variants of the 6502===
 
===Other variants of the 6502===
 +
 
====MOS 6510====
 
====MOS 6510====
 
A 6502 with an 8-bit bi-directional I/O port with the data direction register at address $00 and the port itself at address $01. However all 8 bits were only brought out to actual pins on the 6510-1 and 6510-2 variants, the 6510 only brought out the first 6 bits to pins. The 6510 was used in the [[Commodore 64]] where the main usage of the i/o port was to manage bank-switching (you could switch between ROM and RAM banks, for example). In the C64 the i/o port also controlled the electric motor of the tape recorder. The main reason for using this variant CPU appears to be that it saved the use of a separate [[6522]] VIA chip. The 6510 was also used in some other Commodore computers.
 
A 6502 with an 8-bit bi-directional I/O port with the data direction register at address $00 and the port itself at address $01. However all 8 bits were only brought out to actual pins on the 6510-1 and 6510-2 variants, the 6510 only brought out the first 6 bits to pins. The 6510 was used in the [[Commodore 64]] where the main usage of the i/o port was to manage bank-switching (you could switch between ROM and RAM banks, for example). In the C64 the i/o port also controlled the electric motor of the tape recorder. The main reason for using this variant CPU appears to be that it saved the use of a separate [[6522]] VIA chip. The 6510 was also used in some other Commodore computers.
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* https://en.wikipedia.org/wiki/Ricoh_2A03
 
* https://en.wikipedia.org/wiki/Ricoh_2A03
 
* http://www.cpu-zone.com/moscpu.htm
 
* http://www.cpu-zone.com/moscpu.htm
 +
* http://www.pagetable.com/?p=406
 +
* http://www.visual6502.org/wiki/index.php?title=650X_Schematic_Notes
 +
* http://users.telenet.be/kim1-6502/6502/hwman.html
 
[[Category:Microprocessors]]
 
[[Category:Microprocessors]]

Revision as of 17:44, 6 February 2016

Introduction

The MOS Technology 6502 is an 8-bit microprocessor that was designed by Chuck Peddle and Bill Mensch for MOS Technology in 1975. When it was introduced at around $25 it was the least expensive full-featured CPU on the market by a considerable margin, costing less than one-sixth the price of competing designs from larger companies such as Motorola and Intel. It was nevertheless faster than most of them, and, along with the Zilog Z80, sparked a series of computer projects that would eventually result in the home computer revolution of the 1980s.

It was widely used in Apple, Atari and BBC computers, plus of course Commodore, the company which eventually bought out MOS Technology.

MOS 6502AD 4585 top.jpg

The original NMOS 6502 turned out to have unusually few bugs during the development cycle, unlike some competitors, but there were still a small number of quirks that occasionally created trouble. An early bug was the malfunctioning 'ROR' instruction on pre-June 1976 CPUs. The instruction basically behaved like 'ASL' (Arithmetic Shift Left). Due to this problem the ROR instruction was only documented as "will be available on MCS650X microprocessors after June, 1976". Very early computers like the KIM-1 produced in 1975 were fitted with 6502 CPUs with the ROR bug.

A more longer lasting issue (affecting all NMOS 6502 CPUs) was the 'JMP ($xxFF)' bug. This is a jump to an indirect address, where the LSB of the destination address is in location $xxFF ('xx' can be whatever), and the MSB of the destination address is in location $xy00, where xy = xx+1. The bug is that in the case where the LSB byte is in the last address of a page (as indicated by the FF) the MSB is not read from the first byte of the next page but instead it's read from the first byte of the current page. So, if we have JMP ($05FF) the address should be composed of an LSB from $05FF and an MSB from $0600. Instead the MSB is read from $0500. This bug would be rare enough that a user may never be hit by it, particularly when using an assembler which knew about the bug and could detect a problematic address.

The CMOS version

The JMP bug, and a couple of others, were removed when the processor was redesigned using CMOS instead of NMOS. The CMOS version was designed by Bill Mensch (one of the original designers of the 6800 and the NMOS 6502). It was licensed to many different companies for production, where some of them would use slightly different designs to fit their specific needs. The most well-known versions are the Rockwell 65C02 and Western Design Center (WDC) 65C02. Other variants were made by Synertek[1] and GTE (the GTE version worked well as a drop-in replacement for the NMOS 6502 even in older Apple II computers, although later Apple would use Rockwell 65C02 chips in the Apple IIe and IIc models). WDC continued to design other variants of the 65C02 and are still at it as of 2014. There were other manufacturers as well, including but not limited to NCR, California Micro Devices, and Ricoh. Ricoh made a variant for the Nintendo game system, this version missed the BCD instructions - presumably never needed for Nintendo games.

[1]Synertek and Rockwell were also second-source vendors of the NMOS 6502

Other variants of the 6502

MOS 6510

A 6502 with an 8-bit bi-directional I/O port with the data direction register at address $00 and the port itself at address $01. However all 8 bits were only brought out to actual pins on the 6510-1 and 6510-2 variants, the 6510 only brought out the first 6 bits to pins. The 6510 was used in the Commodore 64 where the main usage of the i/o port was to manage bank-switching (you could switch between ROM and RAM banks, for example). In the C64 the i/o port also controlled the electric motor of the tape recorder. The main reason for using this variant CPU appears to be that it saved the use of a separate 6522 VIA chip. The 6510 was also used in some other Commodore computers.

The 6510 series also used a tri-state address bus, unlike the original NMOS 6502.

Current status of the 6502

WDC continues production and licensing of the 65C02 to this day, in 44-pin PLCC packages as well as the good old 40-pin DIP variant, but now it runs at up to 14MHz (conservatively. 20MHz is easily achieavable and 25MHz has also been reported, when used with components that can keep up.) WDC also licenses 65C02 cores that run up to 200MHz. The 65C02 (including cores) still sells in hundreds of million units per year as of 2012, according to the WDC homepage. There's probably one or more 65C02 in your car, unless it's as old as my car. If you have an implanted heart defibrillator or a pacemaker then you probably (and certainly if it's a defibrillator) have a 65C02 inside your body, the only (AFAIK) processor so far approved for human body implants.

References

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