Difference between revisions of "MASSBUS"
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A variety of controllers existed to connect MASSBUS devices to various kinds of DEC systems: the [[RH10]] for the [[PDP-10]], the [[RH20]] for the [[KL10]], the [[RH11]] for the [[UNIBUS]] (usually on a [[PDP-11]]), the [[RH70]] for the [[PDP-11/70]], the [[RH750]] for the VAX-11/75x, and the [[RH780]] for the [[Synchronous Backplane Interconnect]] bus found on VAX-11/78x, VAX 86xx, etc. | A variety of controllers existed to connect MASSBUS devices to various kinds of DEC systems: the [[RH10]] for the [[PDP-10]], the [[RH20]] for the [[KL10]], the [[RH11]] for the [[UNIBUS]] (usually on a [[PDP-11]]), the [[RH70]] for the [[PDP-11/70]], the [[RH750]] for the VAX-11/75x, and the [[RH780]] for the [[Synchronous Backplane Interconnect]] bus found on VAX-11/78x, VAX 86xx, etc. | ||
| − | The MASSBUS contained two separate sections | + | The MASSBUS contained two separate sections: an asynchronous control section, and a synchronous data transfer section. The two sections operate completely independently. The control section is used to allow the [[CPU]] access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bit and 16-bit (later 32-bit) architectures. |
Revision as of 17:07, 7 November 2016
The MASSBUS was a high-speed I/O bus devised by DEC, and used to connect DEC systems to high-speed disk drives and tape controllers such as the RP04, RP06, TM02 and TM03. A single MASSBUS can contain up to 8 entities.
A variety of controllers existed to connect MASSBUS devices to various kinds of DEC systems: the RH10 for the PDP-10, the RH20 for the KL10, the RH11 for the UNIBUS (usually on a PDP-11), the RH70 for the PDP-11/70, the RH750 for the VAX-11/75x, and the RH780 for the Synchronous Backplane Interconnect bus found on VAX-11/78x, VAX 86xx, etc.
The MASSBUS contained two separate sections: an asynchronous control section, and a synchronous data transfer section. The two sections operate completely independently. The control section is used to allow the CPU access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bit and 16-bit (later 32-bit) architectures.
