Difference between revisions of "PDP-10 memories"
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There were three generations of [[main memory]] systems for the [[PDP-10]]; the first two with the so-called external memory bus, in 18- and 22-bit [[address]] forms (for the [[KA10]]. and [[KI10]] and early [[KL10]], respectively), and the internal 'S-bus' (for the later KL10). (Memory for the [[KS10]], which was ''sui generis'', is not covered here.) | There were three generations of [[main memory]] systems for the [[PDP-10]]; the first two with the so-called external memory bus, in 18- and 22-bit [[address]] forms (for the [[KA10]]. and [[KI10]] and early [[KL10]], respectively), and the internal 'S-bus' (for the later KL10). (Memory for the [[KS10]], which was ''sui generis'', is not covered here.) | ||
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| + | All except the MF20 were [[core memory]], and supported some level of [[interleaving]]. | ||
18-bit external: | 18-bit external: | ||
Revision as of 01:26, 6 March 2019
There were three generations of main memory systems for the PDP-10; the first two with the so-called external memory bus, in 18- and 22-bit address forms (for the KA10. and KI10 and early KL10, respectively), and the internal 'S-bus' (for the later KL10). (Memory for the KS10, which was sui generis, is not covered here.)
All except the MF20 were core memory, and supported some level of interleaving.
18-bit external:
22-bit external:
Internal:
The first two groups are all multi-port memory (generally 4 ports per memory system); the CPU uses one port, the others are used by channels for mass storage such as disks.
