Difference between revisions of "MD10 core memory"
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| − | The '''MD-10''' was a [[core memory|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW | + | The '''MD-10''' was a [[core memory|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW; the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form. |
It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | ||
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| + | Each port on each module could be independently set for its address, and for two-way [[interleaving]] (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34. | ||
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| + | Internal interleaving (among modules in a single MD10) is not productive; the whole MD10 is tied up whenever any module is active. | ||
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| + | Each port and each module can independently be completely disabled (i.e. all modules from a single port, or all ports from a single module; but not a single module from a single port). | ||
[[Category: PDP-10 memories]] | [[Category: PDP-10 memories]] | ||
Revision as of 03:11, 6 March 2019
The MD-10 was a core main memory system for the early PDP-10s, principally the KA10. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW; the cycle time is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit address form.
It was a multi-port memory, with 4 ports per memory system: the CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.
Each port on each module could be independently set for its address, and for two-way interleaving (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34.
Internal interleaving (among modules in a single MD10) is not productive; the whole MD10 is tied up whenever any module is active.
Each port and each module can independently be completely disabled (i.e. all modules from a single port, or all ports from a single module; but not a single module from a single port).
