Difference between revisions of "ME10 core memory"
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| − | The '''ME10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An ME10 contained 16KW | + | The '''ME10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; [[parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] pf .55 µseconds and a [[cycle time]] of 1.0 µseconds. |
It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | ||
Revision as of 01:47, 10 March 2019
The ME10 was a core main memory system for the mid-period PDP-10s, principally the KI10. It connected to the so-called external memory bus of either the 18-bit or 22-bit address form; parity is provided to protect the memory contents. An ME10 contained 16KW; it had an access time pf .55 µseconds and a cycle time of 1.0 µseconds.
It was a multi-port memory, with 4 ports per memory system: each port can be independently disabled. The CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.
Each port could be independently set for its address, and for either 2- or 4-way interleaving (using address bits 21 and 35, and bits 20 and 34, respectively).
