Difference between revisions of "KEF11-B CIS chip"
From Computer History Wiki
m (typo) |
m (+link DIP) |
||
| (One intermediate revision by the same user not shown) | |||
| Line 3: | Line 3: | ||
The '''KEF11-B CIS chip''' is an option for some [[PDP-11]] [[Central Processing Unit|CPU]] [[printed circuit board|boards]] which use the [[F-11 chip set]]; it implements the [[PDP-11 Commercial Instruction Set]]. | The '''KEF11-B CIS chip''' is an option for some [[PDP-11]] [[Central Processing Unit|CPU]] [[printed circuit board|boards]] which use the [[F-11 chip set]]; it implements the [[PDP-11 Commercial Instruction Set]]. | ||
| − | It consists of six [[integrated circuit|chips]] containing additional [[microcode]], on a large dual carrier. Due to its large size, not all the [[KDF11 CPUs]] can use it and the [[KEF11-A floating point chip]] at the same time; the [[KDF11-A CPU]] is too small to hold them both simultaneously. | + | It consists of six [[integrated circuit|chips]] containing additional [[microcode]], on a large dual [[Dual Inline Package|DIP]] carrier. Due to its large physical size, not all the [[KDF11 CPUs]] can use it and the [[KEF11-A floating point chip]] at the same time; the [[KDF11-A CPU]] is too small to hold them both simultaneously. |
{{semi-stub}} | {{semi-stub}} | ||
| − | [[Category: PDP-11 Processors | + | [[Category: PDP-11 Processors]] |
Latest revision as of 17:57, 30 May 2021
The KEF11-B CIS chip is an option for some PDP-11 CPU boards which use the F-11 chip set; it implements the PDP-11 Commercial Instruction Set.
It consists of six chips containing additional microcode, on a large dual DIP carrier. Due to its large physical size, not all the KDF11 CPUs can use it and the KEF11-A floating point chip at the same time; the KDF11-A CPU is too small to hold them both simultaneously.
