Difference between revisions of "Cycle time"
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The DATIP [[bus]] cycles of the [[UNIBUS]] and [[QBUS]] were designed to exploit this timing gain. | The DATIP [[bus]] cycles of the [[UNIBUS]] and [[QBUS]] were designed to exploit this timing gain. | ||
| − | In [[Dynamic RAM|DRAM]] memories, if the memory is in the middle of a [[refresh]] cycle when the request arrives, that can delay the memory's response - and thus the cycle time for that particular cycle. | + | In [[Dynamic RAM|DRAM]] memories, if the memory is in the middle of a [[memory refresh]] cycle when the request arrives, that can delay the memory's response - and thus the cycle time for that particular cycle. |
| − | {{stub}} | + | ==See also== |
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| + | * [[Access time]] | ||
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| + | {{semi-stub}} | ||
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| + | [[Category: Memory Basics]] | ||
Latest revision as of 01:11, 20 September 2022
In main memory, the cycle time of the memory is the time period between the start of one access cycle, and the point in time when the memory is ready to accept another one. Depending on the technology used for the memory, it may or may not be the same for read and write cycles.
In core memory, since reading is inherently a destructive process (so that before a memory bank is ready to move on to the next cycle, it must first re-write the data back into the location which was read out), the two may be different. An ordinary write cycle actually usually takes the same amount of time as a read cycle, since the memory has to be cleared (i.e. read) before it can be written to. However, if a write cycle is directed to a location which was just read, it may be possible to skip both the write-back of the read, and the clear of the write, thereby reducing the time for both.
The DATIP bus cycles of the UNIBUS and QBUS were designed to exploit this timing gain.
In DRAM memories, if the memory is in the middle of a memory refresh cycle when the request arrives, that can delay the memory's response - and thus the cycle time for that particular cycle.
