Difference between revisions of "Memory refresh"
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| − | ''' | + | '''Memory refresh''' is a fundamental part of the operation of all [[memory]] technologies which uses storage of groups of [[electron]]s to hold data. Over time that charge dissipates as the electrons slowly leak away, so they must periodically be 'refreshed' on a regular basis, or the data will be lost. |
| − | To do this, the data in the cells is read out, and then re-written. This is not done with normal read and write operations, since that would take too long (below). Instead, refresh makes use of the fact that in a DRAM, the cells are in a square (normally) array; to do the refresh, an entire row or column is simultaneously read into a special array of [[latch]]es inside the DRAM [[integrated circuit]], and then written back from there. This avoids having to move the data in and out of the chip, which would inevitably be slower since there are many fewer signal paths in and out of the chip. | + | Although historical technologies used in [[main memory]], such as the [[Williams tube]], had to deal with this, it is now mostly an issue with [[Dynamic RAM]] memory. |
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| + | DRAM consists of an [[array]] of small [[capacitor]]s (one for each 'cell', which can store one [[bit]]), which use the presence or absence of a stored charge in the capacitor to indicate the value of the bit stored in that cell. Those cells holding a charge must periodically be refreshed, or the values of those bits will be lost. | ||
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| + | To do this, the data in the cells is read out, and then re-written. This is not done with normal read and write operations, since that would take too long (below). | ||
| + | |||
| + | Instead, refresh makes use of the fact that in a DRAM, the cells are in a square (normally) array; to do the refresh, an entire row or column is simultaneously read into a special array of [[latch]]es inside the DRAM [[integrated circuit]], and then written back from there. This avoids having to move the data in and out of the chip, which would inevitably be slower since there are many fewer signal paths in and out of the chip. | ||
Generally one row or column is done at a time, with a pause before the next one is done; since the memory cannot respond to requests to read or write data while the refresh is happening, this minimizes the impact of any particular refresh cycle - although the total overhead of refresh (normally a few % of the overall time) is not changed by the use of the pauses. | Generally one row or column is done at a time, with a pause before the next one is done; since the memory cannot respond to requests to read or write data while the refresh is happening, this minimizes the impact of any particular refresh cycle - although the total overhead of refresh (normally a few % of the overall time) is not changed by the use of the pauses. | ||
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The time between consecutive refresh operations to a given cell is typically in the low numbers of milliseconds. | The time between consecutive refresh operations to a given cell is typically in the low numbers of milliseconds. | ||
| − | {{stub}} | + | {{semi-stub}} |
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| + | ==See also== | ||
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| + | * [[Display refresh]] | ||
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| + | [[Category: Memory Basics]] | ||
Latest revision as of 01:15, 20 September 2022
Memory refresh is a fundamental part of the operation of all memory technologies which uses storage of groups of electrons to hold data. Over time that charge dissipates as the electrons slowly leak away, so they must periodically be 'refreshed' on a regular basis, or the data will be lost.
Although historical technologies used in main memory, such as the Williams tube, had to deal with this, it is now mostly an issue with Dynamic RAM memory.
DRAM consists of an array of small capacitors (one for each 'cell', which can store one bit), which use the presence or absence of a stored charge in the capacitor to indicate the value of the bit stored in that cell. Those cells holding a charge must periodically be refreshed, or the values of those bits will be lost.
To do this, the data in the cells is read out, and then re-written. This is not done with normal read and write operations, since that would take too long (below).
Instead, refresh makes use of the fact that in a DRAM, the cells are in a square (normally) array; to do the refresh, an entire row or column is simultaneously read into a special array of latches inside the DRAM integrated circuit, and then written back from there. This avoids having to move the data in and out of the chip, which would inevitably be slower since there are many fewer signal paths in and out of the chip.
Generally one row or column is done at a time, with a pause before the next one is done; since the memory cannot respond to requests to read or write data while the refresh is happening, this minimizes the impact of any particular refresh cycle - although the total overhead of refresh (normally a few % of the overall time) is not changed by the use of the pauses.
The time between consecutive refresh operations to a given cell is typically in the low numbers of milliseconds.
