Difference between revisions of "FP11-B Floating-Point Processor"

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The '''FP11-B''' was a [[Floating point processor|FPP]] used in the [[PDP-11/45]] and [[PDP-11/70]] computers (KB11-A and KB11-B CPU variants thereof, respectively); it operated in parallel with the main processor, so that two instructions (one floating point, one regular) could be processed at the same time.
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The '''FP11-B''' was a [[Floating point processor|FPP]] used in the [[PDP-11/45]] and [[PDP-11/70]] computers ([[KB11-A CPU|KB11-A]] and [[KB11-B CPU|KB11-B]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was the progenitor of the semi-standard [[FP11 floating point]] used in many [[PDP-11]]s.
  
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It supported short (32 bit) and long (64 bit) floating point numbers; both forms used an 8 bit exponent (in 'excess 0200' notation, giving an exponent range of +127. to -128.), a sign bit, and the remaining bits were the fractional part. A state bit controlled whether the FP11-B operated in short or long mode.
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It operated in parallel with the main processor, so that two instructions (one floating point, one regular) could be processed at the same time; unlike the later [[FP11-C Floating-Point Processor]] for these machines, it ran entirely [[asynchronous]]ly to the main CPU, and used a clock which was not synchronized to the basic CPU's clock.  
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The FP11-B contained 6 internal registers, each capable of holding either a short or long floating point value.
 
  
 
==Implementation==
 
==Implementation==
  
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The FP11-B runs entirely asynchronously to the main CPU; it used a clock which is not synchronized to the basic CPU's clock. It plugged into special pre-wired slots in the CPU's [[backplane]], and included the following boards:
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It plugged into special pre-wired slots in the CPU's [[backplane]], and included the following boards:
  
 
* M8112 ROM and ROM Control
 
* M8112 ROM and ROM Control
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* M8115 Fraction Data Path - Low Order
 
* M8115 Fraction Data Path - Low Order
  
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{{PDP-11}}
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==External links==
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* [http://www.bitsavers.org/pdf/dec/pdp11/1145/EK-FP11-MM-003_FP11-B_Floating-Point_Processor_Maintenance_Manual_1974.pdf FP11-B floating point processor maintenance manual] (EK-FP11-MM-003)
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* [http://www.bitsavers.org/pdf/dec/pdp11/1145/PDP11_FP11-B_Floating-Point_Processor_Engineering_Drawings_Rev_A_Jul72.pdf FP11-B floating point processor engineering drawings]
  
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[[Category:DEC processors]]
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[[Category: PDP-11 UNIBUS Processors]]
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[[Category:UNIBUS processors]]
 

Latest revision as of 01:17, 13 October 2022

The FP11-B was a FPP used in the PDP-11/45 and PDP-11/70 computers (KB11-A and KB11-B CPU variants thereof, respectively); it was the progenitor of the semi-standard FP11 floating point used in many PDP-11s.

It operated in parallel with the main processor, so that two instructions (one floating point, one regular) could be processed at the same time; unlike the later FP11-C Floating-Point Processor for these machines, it ran entirely asynchronously to the main CPU, and used a clock which was not synchronized to the basic CPU's clock.

Implementation

It plugged into special pre-wired slots in the CPU's backplane, and included the following boards:

  • M8112 ROM and ROM Control
  • M8113 Exponent and Data Path
  • M8114 Fraction Data Path - High Order
  • M8115 Fraction Data Path - Low Order

External links

Retrieved from "https://gunkies.org/w/index.php?title=FP11-B_Floating-Point_Processor&oldid=27837"