Difference between revisions of "Talk:MIT UNIBUS XGP interface"
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Are those encodings interpreted by the UNIBUS XGP interface, or by the XGP itself? [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 14:10, 31 January 2024 (CET) | Are those encodings interpreted by the UNIBUS XGP interface, or by the XGP itself? [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 14:10, 31 January 2024 (CET) | ||
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| + | : I'm not sure. I found a file that seem to describe an interface, maybe the CMU one. It says "''The BIT CLocK is active only when data is actually being sent to the XGP. Its most direct purpose is to clock the next video bit into the VIDEO flip-flop from either the right end of the SR (Sheet 8) in CHAR or IMAGE modes, or from the BLACK/WHITE flip-flop (Sheet 8) in VECTor mode. This VIDEO is actually nothing more or less than the z-axis input to he CRT in the printer.''" (SR is a shift register.) Thus it seems to me most or all logic is in the interface. The description of the SAIL interface seems similar; there's a direct feed to the CRT. [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 14:52, 31 January 2024 (CET) | ||
Revision as of 14:52, 31 January 2024
SAIL hardware interface?
I found these SUDS drawings dated 1973, in an archived ITS directory called "XGP". I was hoping they would explain MIT's hardware interface, but they don't seem to match the PDP-11 software. Since I see references to IOBUS, CONO, CONI, I suspect they are for SAIL's XGP interface. I converted the files to SVG format; feel free to take a look. http://lars.nocrew.org/tmp/xgp-drawings/ Larsbrinkhoff (talk) 07:29, 30 January 2024 (CET)
- I am 99.4% sure they are for the PDP-10 I/O bus (not only a reference in drawing 'COMND' to "CONO SET", and also to "CONI" in 'STATUS', but if you look at the way "DEVSEL" is generated, on 'COMND' - and neither there or anywhere else any reference to MSYN or SSYN), so not the UNIBUS interface from MIT (or CMU). I designed several UNIBUS interfaces, and this ain't one! Jnc (talk) 15:06, 30 January 2024 (CET)
Data encoding
Are those encodings interpreted by the UNIBUS XGP interface, or by the XGP itself? Jnc (talk) 14:10, 31 January 2024 (CET)
- I'm not sure. I found a file that seem to describe an interface, maybe the CMU one. It says "The BIT CLocK is active only when data is actually being sent to the XGP. Its most direct purpose is to clock the next video bit into the VIDEO flip-flop from either the right end of the SR (Sheet 8) in CHAR or IMAGE modes, or from the BLACK/WHITE flip-flop (Sheet 8) in VECTor mode. This VIDEO is actually nothing more or less than the z-axis input to he CRT in the printer." (SR is a shift register.) Thus it seems to me most or all logic is in the interface. The description of the SAIL interface seems similar; there's a direct feed to the CRT. Larsbrinkhoff (talk) 14:52, 31 January 2024 (CET)
