Difference between revisions of "BCC 500"
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[[Image:BCC-500_1.jpg|300px|right|thumb|BCC 500]] | [[Image:BCC-500_1.jpg|300px|right|thumb|BCC 500]] | ||
| − | The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]]. When the company went bankrupt, the prototype went to Hawaii and was successfully deployed as an [[ARPANET]] host. It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]]. | + | The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]]. When the company went bankrupt, the prototype went to Hawaii and was successfully deployed as an [[ARPANET]] host until 1980. It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]]. |
The computer consists of six independent microcoded processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory. The microcode implements a machine code with a 6-bit opcode and 18-bit address field. Two of the processors have expanded hardware capabilities and run user code. The other four are each responsible for implementing their own part of the operating system; part in microcode and part in macrocode. | The computer consists of six independent microcoded processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory. The microcode implements a machine code with a 6-bit opcode and 18-bit address field. Two of the processors have expanded hardware capabilities and run user code. The other four are each responsible for implementing their own part of the operating system; part in microcode and part in macrocode. | ||
Revision as of 18:01, 7 March 2024
The BCC 500 was a computer made by the Berkeley Computer Corporation. When the company went bankrupt, the prototype went to Hawaii and was successfully deployed as an ARPANET host until 1980. It was also the hub of the ALOHA network which inspired Ethernet.
The computer consists of six independent microcoded processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory. The microcode implements a machine code with a 6-bit opcode and 18-bit address field. Two of the processors have expanded hardware capabilities and run user code. The other four are each responsible for implementing their own part of the operating system; part in microcode and part in macrocode.
