Difference between revisions of "IAS computer"
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| − | The '''IAS computer''' (sometimes called the '''IAS machine'''; it seems not to have had a formal name, although some later contemporary documents call it 'MANIAC', a name used by the Los Alamos copy) was a very early [[electronic]] [[program]]mable [[computer]]. The group that designed and built it began the task in June, 1946, and it | + | The '''IAS computer''' (sometimes called the '''IAS machine'''; it seems not to have had a formal name, although some later contemporary documents call it 'MANIAC', a name used by the Los Alamos copy) was a very early [[electronic]] [[program]]mable [[computer]]. The group that designed and built it began the task in June, 1946, initial operation began in the fall of 1950, and it was formally dedicated on 10 June, 1952. Its most significant contribution was the vast list of first-generation computers, both in the US, and around the world, which were copies of it (below). |
The group, the '''Electronic Computer Project''' (ECP), was assembled by [[John von Neumann]] at the [[Institute for Avanced Study]] (IAS) at Princeton (von Neumann's base institution at the time). This machine became his focus after his involvement in the planning for, and design of, the [[EDVAC]] had enlightened him to the promise of the field. (He broke off his connection to [[John Mauchly]], and especially [[J. Presper Eckert]], because they were focused on starting a business, the eventual [[Eckert–Mauchly Computer Corporation]], and he wished to make all his work public - as the many copies of the IAS computer testified.) | The group, the '''Electronic Computer Project''' (ECP), was assembled by [[John von Neumann]] at the [[Institute for Avanced Study]] (IAS) at Princeton (von Neumann's base institution at the time). This machine became his focus after his involvement in the planning for, and design of, the [[EDVAC]] had enlightened him to the promise of the field. (He broke off his connection to [[John Mauchly]], and especially [[J. Presper Eckert]], because they were focused on starting a business, the eventual [[Eckert–Mauchly Computer Corporation]], and he wished to make all his work public - as the many copies of the IAS computer testified.) | ||
| − | The engineers on the ECP team initially included Julian Bigelow (Chief Engineer; replaced mid-way with initial team-member James Pomerene), John Davis, Robert Shaw, Ralph Slutz, and Willis Ware; Morris Rubinoff and | + | The engineers on the ECP team initially included Julian Bigelow (Chief Engineer; replaced mid-way with initial team-member James Pomerene), John Davis, Robert Shaw, Ralph Slutz, and Willis Ware; Morris Rubinoff and Richard Snyder joined later. Other members of the team included Arthur Burks, Jule Charney, Hewitt Crane, N. Emslie, Gerald Estrin, E. Frei, Herman Goldstine, T. Hildebrandt, G. Kent, W. Melville, J. Rosenberg, Morris Rubinoff, Richard L. Snyder, and others. Their work was widely distributed via progress reports, which were circulated extensively. The IAS closed the ECP in 1957-58 (the exact date is uncertain); apparently because as an organization the IAS was uncomfortable with such an essentially practical effort. The personnel then scattered, taking their knowledge with them; many became leading lights on other early computers. |
==Technical details== | ==Technical details== | ||
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Not one of the many, many later books which describe the IAS machine (below) give complete coverage of its [[architecture]]. This description is mostly gleaned from the ''Final Progress Report'' (below); the [[instruction set]] is enumerated at the end of that, and is given below. | Not one of the many, many later books which describe the IAS machine (below) give complete coverage of its [[architecture]]. This description is mostly gleaned from the ''Final Progress Report'' (below); the [[instruction set]] is enumerated at the end of that, and is given below. | ||
| − | It eventually used 40 [[Williams tube]]s for its [[main memory]] (after the [[Selectron]] project failed to produce usable memory). | + | It eventually used 40 [[Williams tube]]s for its [[main memory]] (after the [[Selectron]] project failed to produce usable memory, although a later copy used them). They contained 1K words in total, each tube using a 32x32 [[array]]. (Although this memory had to be [[memory refresh|refreshed]], refresh cycles could be combined with read/write operations when possible.) The [[logic]] was constructed using [[vacuum tube]]s (although only about 3,000; many fewer than the [[ENIAC]]). |
It was an [[asynchronous]] [[parallel computer]] internally, using 40-[[bit]] [[word]]s. It used [[binary]], with the sign bit at the left (and [[two's complement]]), and the binary point between it and the next bit; i.e. words can represent values between 1 and -1. | It was an [[asynchronous]] [[parallel computer]] internally, using 40-[[bit]] [[word]]s. It used [[binary]], with the sign bit at the left (and [[two's complement]]), and the binary point between it and the next bit; i.e. words can represent values between 1 and -1. | ||
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It had instructions to perform multiplication and division, but no special hardware; both were performed a bit at a time, with shifting (performed with the sub-registers described above) and addition/subtraction. (Throughout the contemporary documentation, a great amount of attention is paid to the details of the arithmetic - as one might expect of a design in which John von Neumann was involved!) | It had instructions to perform multiplication and division, but no special hardware; both were performed a bit at a time, with shifting (performed with the sub-registers described above) and addition/subtraction. (Throughout the contemporary documentation, a great amount of attention is paid to the details of the arithmetic - as one might expect of a design in which John von Neumann was involved!) | ||
| − | It was eventually given | + | It was eventually (June, 1953) given an IAS-built [[drum]] of 2K words; a 12K one from [[Engineering Research Associates|ERA]] was later (1955) installed. [[Input/output|I/O]] was on [[paper tape]] initially, later switched to [[punched card]]s, and supplemented with a 7" [[CRT]] for [[graphics]] output. |
===Instruction set=== | ===Instruction set=== | ||
| − | Two instructions were stored in each word, referred to as the 'first' (left) and 'second' (right) 'phases'; executed in that order. A few instructions could be executed in the left | + | Two instructions were stored in each word, referred to as the 'first' (left) and 'second' (right) 'phases'; executed in that order. A few instructions could be executed in the left phase only, and one in the right only; such limitations are given in the table below (a blank entry means 'either'). |
| − | The 'step digit', bit 11, may be 0 ([[halt]] after executing the instruction) or 1 in many instructions. If so, it is indicated by an 'S' in 'bits' column (and also in the numeric opcode). The 'clear digit', bit 18, is available in some instructions; if so, it is indicated by a 'C' in the 'bits' column (and will set the appropriate bit in the numeric opcode). It may be 0 (see 'Comment' for action) or 1 (clear R1 before commencing). | + | The 'step digit', bit 11, may be 0 ([[halt]] after executing the instruction) or 1 in many instructions. If so, it is indicated by an 'S' in 'bits' column (and also in the numeric opcode). "S=1" means it ''must'' be set in that instruction. The 'clear digit', bit 18, is available in some instructions; if so, it is indicated by a 'C' in the 'bits' column (and will set the appropriate bit in the numeric opcode). It may be 0 (see 'Comment' for action) or 1 (clear R1 before commencing). |
Potential [[operand]]s are generally R<sub>1</sub>, R<sub>2</sub>, and R<sup>3</sup> (referred to as "R3" in the table); and the contents ('b') of the memory location (address 'x'). Most instruction (unless otherwise noted) leave b in R3. A detailed description of each instruction is provided on the given page of the ''Final Progress Report''. | Potential [[operand]]s are generally R<sub>1</sub>, R<sub>2</sub>, and R<sup>3</sup> (referred to as "R3" in the table); and the contents ('b') of the memory location (address 'x'). Most instruction (unless otherwise noted) leave b in R3. A detailed description of each instruction is provided on the given page of the ''Final Progress Report''. | ||
{| class="wikitable" | {| class="wikitable" | ||
| − | ! Group !! Opcode !! Name !! Page !! | + | ! Group !! Opcode !! Name !! Page !! Bits !! Phase !! Brief description !! Comment |
|- | |- | ||
| − | | rowspan="8" | {{VerticalTextUp|Summation}} || S712 || Plus clear || 22 || | + | | rowspan="8" | {{VerticalTextUp|Summation}} || S712 || Plus clear || 22 || S || || Load b into R1 |
|- | |- | ||
| − | | S710 || Plus hold || 23 || | + | | S710 || Plus hold || 23 || S || || Add b to R1 |
|- | |- | ||
| − | | S732 || Minus clear || 24 || | + | | S732 || Minus clear || 24 || S || || Load 2-b into R1 |
|- | |- | ||
| − | | S730 || Minus hold || 24 || | + | | S730 || Minus hold || 24 || S || || Subtract b from R1 |
|- | |- | ||
| S752 || Plus absolute clear || 25 || S || || Load abs(b) into R1 | | S752 || Plus absolute clear || 25 || S || || Load abs(b) into R1 | ||
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* WEIZAC (Weizmann Institute, Israel) - October, 1955 | * WEIZAC (Weizmann Institute, Israel) - October, 1955 | ||
| − | The [[IBM 701]] was apparently a 'cleaned up' copy as well, as were the [[EDB-2]] and [[EDB-3]] families built in Sweden from 1957 on, and the FACOM 201 (a copy of the MUSASINO-1) produced by Fujitsu from 1960. | + | The [[IBM 701]] was apparently a 'cleaned up' copy as well (a different word length, with half-word addresses), as were the [[EDB-2]] and [[EDB-3]] families built in Sweden from 1957 on, and the FACOM 201 (a copy of the MUSASINO-1) produced by Fujitsu from 1960. |
Several other machines (such as the [[BESM 1]]) were built after close study of the IAS computer's documentation (and in the BESM 1's case, that of the BESK as well), but were not copies of it. | Several other machines (such as the [[BESM 1]]) were built after close study of the IAS computer's documentation (and in the BESM 1's case, that of the BESK as well), but were not copies of it. | ||
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* Herman H. Goldstine, ''The Computer from Pascal to von Neumann'', Princeton University, Princeton, 1972 - contains details of the entire effort, in which Goldstine participated | * Herman H. Goldstine, ''The Computer from Pascal to von Neumann'', Princeton University, Princeton, 1972 - contains details of the entire effort, in which Goldstine participated | ||
| − | * William Aspray, ''John von Neumann and the Origins of Modern Computing'', MIT Press, Cambridge, 1990 | + | * William Aspray, ''John von Neumann and the Origins of Modern Computing'', MIT Press, Cambridge, 1990 - not much technical detail, but a good overall history, and a lot about problem areas the machine was used for |
* Julian Bigelow ''Computer Development at the Institute for Advanced Study''; pp. 291-310 in Nicholas Metropolis, Jack Howlett, Gian-Carlo Rota (editors), [https://www.sciencedirect.com/book/9780124916500/a-history-of-computing-in-the-twentieth-century ''A History of Computing in the Twentieth Century''], Academic Press, New York, 1980 - the IAS computer is covered in the first section of Part IV, but with a focus on the electrical engineering; many descendants are covered in detail in other sections | * Julian Bigelow ''Computer Development at the Institute for Advanced Study''; pp. 291-310 in Nicholas Metropolis, Jack Howlett, Gian-Carlo Rota (editors), [https://www.sciencedirect.com/book/9780124916500/a-history-of-computing-in-the-twentieth-century ''A History of Computing in the Twentieth Century''], Academic Press, New York, 1980 - the IAS computer is covered in the first section of Part IV, but with a focus on the electrical engineering; many descendants are covered in detail in other sections | ||
* George Dyson, ''Turing's Cathedral: The Origins of the Digital Universe'', Pantheon, New York, 2012 - focused on the creation of this machine at the Institute for Advanced Study | * George Dyson, ''Turing's Cathedral: The Origins of the Digital Universe'', Pantheon, New York, 2012 - focused on the creation of this machine at the Institute for Advanced Study | ||
Revision as of 20:49, 8 April 2024
The IAS computer (sometimes called the IAS machine; it seems not to have had a formal name, although some later contemporary documents call it 'MANIAC', a name used by the Los Alamos copy) was a very early electronic programmable computer. The group that designed and built it began the task in June, 1946, initial operation began in the fall of 1950, and it was formally dedicated on 10 June, 1952. Its most significant contribution was the vast list of first-generation computers, both in the US, and around the world, which were copies of it (below).
The group, the Electronic Computer Project (ECP), was assembled by John von Neumann at the Institute for Avanced Study (IAS) at Princeton (von Neumann's base institution at the time). This machine became his focus after his involvement in the planning for, and design of, the EDVAC had enlightened him to the promise of the field. (He broke off his connection to John Mauchly, and especially J. Presper Eckert, because they were focused on starting a business, the eventual Eckert–Mauchly Computer Corporation, and he wished to make all his work public - as the many copies of the IAS computer testified.)
The engineers on the ECP team initially included Julian Bigelow (Chief Engineer; replaced mid-way with initial team-member James Pomerene), John Davis, Robert Shaw, Ralph Slutz, and Willis Ware; Morris Rubinoff and Richard Snyder joined later. Other members of the team included Arthur Burks, Jule Charney, Hewitt Crane, N. Emslie, Gerald Estrin, E. Frei, Herman Goldstine, T. Hildebrandt, G. Kent, W. Melville, J. Rosenberg, Morris Rubinoff, Richard L. Snyder, and others. Their work was widely distributed via progress reports, which were circulated extensively. The IAS closed the ECP in 1957-58 (the exact date is uncertain); apparently because as an organization the IAS was uncomfortable with such an essentially practical effort. The personnel then scattered, taking their knowledge with them; many became leading lights on other early computers.
Contents
Technical details
Not one of the many, many later books which describe the IAS machine (below) give complete coverage of its architecture. This description is mostly gleaned from the Final Progress Report (below); the instruction set is enumerated at the end of that, and is given below.
It eventually used 40 Williams tubes for its main memory (after the Selectron project failed to produce usable memory, although a later copy used them). They contained 1K words in total, each tube using a 32x32 array. (Although this memory had to be refreshed, refresh cycles could be combined with read/write operations when possible.) The logic was constructed using vacuum tubes (although only about 3,000; many fewer than the ENIAC).
It was an asynchronous parallel computer internally, using 40-bit words. It used binary, with the sign bit at the left (and two's complement), and the binary point between it and the next bit; i.e. words can represent values between 1 and -1.
The machine included 3 registers, each 40 bits long:
- RI (also given as R1 in documentation) - the Accumulator; one input to the adder, receives the output from the adder
- RII (also R2) - the Arithmetic Register; used in multiplication and division
- RIII (also R3) - the Memory Register; the other input (possibly complemented, or zeroed) to the adder
Each register is composed internally of a pair of 'sub-registers' (termed "ranks"), denoted as Rn (the "permanent rank") and Rn (the "temporary rank") in contemporary documentation. RI and RII can perform single-bit left and right shifts when copying data from the Rn rank to Rn; an un-shifted copy can take place from Rn to Rn. RIII can also be copied to RII, and RII to RI.
Instructions were 20 bits long, and contained a 10-bit opcode and a 10-bit address. There were about 30 in total.
It had instructions to perform multiplication and division, but no special hardware; both were performed a bit at a time, with shifting (performed with the sub-registers described above) and addition/subtraction. (Throughout the contemporary documentation, a great amount of attention is paid to the details of the arithmetic - as one might expect of a design in which John von Neumann was involved!)
It was eventually (June, 1953) given an IAS-built drum of 2K words; a 12K one from ERA was later (1955) installed. I/O was on paper tape initially, later switched to punched cards, and supplemented with a 7" CRT for graphics output.
Instruction set
Two instructions were stored in each word, referred to as the 'first' (left) and 'second' (right) 'phases'; executed in that order. A few instructions could be executed in the left phase only, and one in the right only; such limitations are given in the table below (a blank entry means 'either').
The 'step digit', bit 11, may be 0 (halt after executing the instruction) or 1 in many instructions. If so, it is indicated by an 'S' in 'bits' column (and also in the numeric opcode). "S=1" means it must be set in that instruction. The 'clear digit', bit 18, is available in some instructions; if so, it is indicated by a 'C' in the 'bits' column (and will set the appropriate bit in the numeric opcode). It may be 0 (see 'Comment' for action) or 1 (clear R1 before commencing).
Potential operands are generally R1, R2, and R3 (referred to as "R3" in the table); and the contents ('b') of the memory location (address 'x'). Most instruction (unless otherwise noted) leave b in R3. A detailed description of each instruction is provided on the given page of the Final Progress Report.
| Group | Opcode | Name | Page | Bits | Phase | Brief description | Comment |
|---|---|---|---|---|---|---|---|
| Summation | S712 | Plus clear | 22 | S | Load b into R1 | ||
| S710 | Plus hold | 23 | S | Add b to R1 | |||
| S732 | Minus clear | 24 | S | Load 2-b into R1 | |||
| S730 | Minus hold | 24 | S | Subtract b from R1 | |||
| S752 | Plus absolute clear | 25 | S | Load abs(b) into R1 | |||
| 750 | Plus absolute hold | 25 | S | Add abs(b) to R1 | |||
| S772 | Minus absolute clear | 26 | S | Load 2-abs(b) into R1 | |||
| S770 | Minus absolute hold | 26 | S | Subtract b from R1 | It is not clear if/how this differs from 'Minus hold' | ||
| Other | S702/700 | Multiply no round off | 27 | SC | Multiply R2 and b; high order result to R1, low order to R2 | If C=0, add the old contents of R1 to the product | |
| S706/704 | Multiply round off | 28 | SC | As previous | Ditto | ||
| S760 | Division | 28 | S | Divide R1 by b; leaves result in R2, twice the remainder in R1 | |||
| S714 | Load RII | 29 | SC | Load R2 | |||
| Trivial | 1650 | Store | 30 | S=1 | Store R1; clear R3 | ||
| 1652 | Store clear | 30 | S=1 | Clear R1, R3, and memory | |||
| S640 | Un-conditional transfer | 31 | Next instruction will be from 'b' (opposite phase from this one, if step bit is set); clear R3 | b is stored in R3 | |||
| S660 | Conditional transfer | 32 | If R1 >= 0, then as above; if < 0, a no-op | ||||
| Special | 1711-1773 | Quick sum | 33 | S=1 | first | See entry in Final Progress Report | |
| Non-memory | S500 | Right shift, no round off | 34 | SC | Shift R1/R2 double-width register right N bits, always retaining sign bit in R1; copy old contents of R2 to R3 | N is given in bits 4-9, and must be > 0 and < 47; if C=0, no effect, if C=1 clear R1 before shift | |
| S504 | Right shift, round off | 35 | SC | Not implemented | |||
| S520 | Left shift | 35 | SC | Shift R1 and R2 independently left N bits, with the sign bit of R1 copied into the low bit of both; copy old contents of R2 to R3 | As for 'right shift, no round off'; but if C=1, R1 is cleared after shift, and the sign bit of R1 is cleared before being copied to R2 | ||
| S510-S572 | R2 to R1 | 36 | S | Same as 'Summation' group, but the operand is in R2, not memory | |||
| Input-output | 1200-1376 | IBM and drum priming | 37 | S | second | See entry in Final Progress Report | S is only recommended |
| 1010 | IBM input to memory | 39 | S=1 | first | Ditto; the second instruction in the word must be a jump to the next instruction | ||
| 1116 | IBM output to [sic] memory | 39 | S=1 | first | Ditto | ||
| 1210-1230 | Drum input to memory | 39 | S=1 | first | Ditto | ||
| 1316-1336 | Drum output from memory | 40 | S=1 | first | Ditto |
NOTE: the document uses "digit" where we would now say 'bit'.
The operation codes are given in a table in the Final Progress Report, but not in numeric form; and the column for each bit in the opcode has an individual name, not a number. It is not known if the columns are in numeric order; if they are, the step bit is in the bit number indicated elsewhere in the document (11), but the clear digit bit is not (it is given elsewhere as bit 18, but is 19 in the table). They are given above in octal, as if the bit columns in the Final Progress Report are in numeric order. The bit columns (numbered by apparent value, based on position) are labelled:
| Bit | '0' Value | '1' Value |
|---|---|---|
| 11 | No step | Step |
| 12 | Ext. | Int. |
| 13 | Arith. | Wms. |
| 14 | AT | NAT |
| 15 | # | Abs. |
| 16 | +R | -L |
| 17 | x/÷ | ∑ |
| 18 | No RO | RO |
| 19 | Hold | Clear |
| 20 | Spare | |
Copies
As mentioned, many copies of it were built, early on (and a few later), some with the help of people who had worked on the IAS machine. The faithfulness of the copies varied from machine to machine (apparently including a last one, built with transistors); the later ones used core memory. The list of the US ones, with their dates of completion, is:
- AVIDAC(Argonne) - January, 1953
- CYCLONE (Iowa State University) - July, 1959
- ILLIAC (Illinois) - September, 1952
- JOHNNIAC (Rand) - March, 1954
- MANIAC (Los Alamos) - March, 1952 (slightly before the original)
- MISTIC (Michigan State University) - November, 1957 (a copy of the ILLIAC)
- ORACLE (Oak Ridge) - September, 1953
- ORDVAC (Aberdeen) - November, 1951
(The MANIAC was said to have been so named in protest against the 'cute' names which had become the fashion.) Elsewhere, they included:
- BESK (Royal Institute of Technology, Sweden) - November, 1953 (included hardware floating point)
- DASK (Academy of Technical Sciences, Denmark) - 1957 (a copy of BESK)
- EDB-1 (Facit, Sweden) - 1957 (another copy of BESK, without floating point)
- MUSASINO-1 (NTT, Japan) - March, 1957
- SARA (SAAB, Sweden) - 1957 (another tweaked copy of BESK)
- SILLIAC (University of Sydney, Australia) - June, 1956
- SMIL (Lund University, Sweden) - June, 1956
- TRASK (Datasystem AB, Sweden) - 1965 (another copy of BESK, using transistors and core)
- WEIZAC (Weizmann Institute, Israel) - October, 1955
The IBM 701 was apparently a 'cleaned up' copy as well (a different word length, with half-word addresses), as were the EDB-2 and EDB-3 families built in Sweden from 1957 on, and the FACOM 201 (a copy of the MUSASINO-1) produced by Fujitsu from 1960.
Several other machines (such as the BESM 1) were built after close study of the IAS computer's documentation (and in the BESM 1's case, that of the BESK as well), but were not copies of it.
Further reading
Books
- Herman H. Goldstine, The Computer from Pascal to von Neumann, Princeton University, Princeton, 1972 - contains details of the entire effort, in which Goldstine participated
- William Aspray, John von Neumann and the Origins of Modern Computing, MIT Press, Cambridge, 1990 - not much technical detail, but a good overall history, and a lot about problem areas the machine was used for
- Julian Bigelow Computer Development at the Institute for Advanced Study; pp. 291-310 in Nicholas Metropolis, Jack Howlett, Gian-Carlo Rota (editors), A History of Computing in the Twentieth Century, Academic Press, New York, 1980 - the IAS computer is covered in the first section of Part IV, but with a focus on the electrical engineering; many descendants are covered in detail in other sections
- George Dyson, Turing's Cathedral: The Origins of the Digital Universe, Pantheon, New York, 2012 - focused on the creation of this machine at the Institute for Advanced Study
- Raul Rojas, Ulf Hashagen, The First Computers: History and Architectures, MIT Press, Cambridge, 2002 - the IAS machine is covered in chapter II/4; no detail of the machine, but interesting coverage of the background and influence
- John Deane, The IAS Computer Family Scrapbook - lists further information sources for each machine
Papers
- Arthur W. Burks, Herman H. Goldstine, John von Neumann, Preliminary discussion of the logical design of an electronic computing instrument, Institute for Advanced Study, Princeton, June, 1946 - thoughts about the design of a computer - before any had ever been built!
- W. H. Ware, The History and Development of the Electronic Computer Project at the Institute for Avanced Study (Rand Report P-377, March, 1953) - includes interesting detail of the electrical engineering design philosophy; implementation details of many of the 'copy' machines; and personnel notes
- Gerald Estrin, A description of the electronic computer at the Institute for Advanced Studies, Proceedings of the 1952 ACM national meeting (Toronto), September 1952 - very complete, but low-level, description
- Nicholas Metropolis, J. Worlton, A Trilogy On Errors in the History of Computing, Los Alamos National Laboratory, Los Alamos, 1972 - contains a section on the mis-identification of the IAS machine as the 'MANIAC'; also historical notes about both machines
External links
- IAS - documentation at Bitsavers (skimpy)
- Final Progress Report on the Physical Realization of an Electronic Computing Instrument - contains a lot of details on the mathematics, and a detailed list of instructions
- Electronic Computer Project
