Difference between revisions of "Synchronous Backplane Interconnect"
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* [http://www.bitsavers.org/pdf/dec/vax/handbook/VAX_Hardware_Handbook_Volume_1_1986.pdf VAX Hardware Handbook Volume 1] - the SBI is covered in detail in Chapter 9 (pp. 321-344 of the PDF) | * [http://www.bitsavers.org/pdf/dec/vax/handbook/VAX_Hardware_Handbook_Volume_1_1986.pdf VAX Hardware Handbook Volume 1] - the SBI is covered in detail in Chapter 9 (pp. 321-344 of the PDF) | ||
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Revision as of 00:46, 8 May 2024
The Synchronous Backplane Interconnect (sometimes given as the acronym, SBI) was the high-speed bus which connected the major functional units (CPU, main memory, I/O adapters, etc), in early VAXen:
It was synchronous, in that everything on the bus happened in fixed time slots; but it was somewhat asynchronous, in that the slots which were part of an operation (e.g. requesting a read; and the data being returned) had no fixed temporal relationship. The slots of different operations may be interleaved; e.g. after a memory read is started in one slot, some other operation might use some of the slots before the one in which the data is returned.
Allocation of slots was done by a fully-distributed arbitration process, among all the functional units attached to the SBI (called 'nexi'). The arbitration is overlaid, temporally, with operation: the selection of which nexus will perform an operation in a following slot is done during the previous slot; during that previous slot, some other operation may have happened. A nexus can be classified as being one of:
- Commander - a nexus that transmits an address and command
- Responder - a nexus that recognizes an address and responds to the accompanying command
- Transmitter - a nexus that drives the SBI lines
- Receiver - a nexus that examines the SBI lines
Obviously, a nexus may appear in different categories over time; e.g. a CPU is a transmitter during a write to memory, and a receiver during a red.
The SBI has 32 data lines, and 28 address lines (addresses name long-words). It can transfer units of 8, 16, 32 ('long-word'), and 64 ('quad-word') bits. Data is protected by parity on the SBI.
In addition to data transfer operations, interrupt operations are also supported.
External links
- VAX-11/780 Hardware User's Guide (EK-11780-UG-001) - the SBI is covered in Section 1.3.2.1, pp. 21-22 of the PDF
- Translation Buffer, Cache and SBI Control Technical Description (EK-MM780-TD-001) - the SBI is covered in Section 1.8.1, pp. 29-31 of the PDF, and Section 2.3, pp. 72-129
- VAX Hardware Handbook Volume 1 - the SBI is covered in detail in Chapter 9 (pp. 321-344 of the PDF)
