Condition codes

Condition codes are a way of recording high-level information about the results of arithmetic operations in a CPU, to allow later conditional branches to divert the control flow in the program, depending on the results of the arithmetic operation.

Combinations of various condition code bits can be interpreted for both two's complement signed computations as well as unsigned. By testing these bits, the complete set of signed and unsigned conditional branches can be produced.

The basic group of condition code bits are:

• Z (Zero) - the result was 0
• N or S (Negative or Sign) - the result was negative
• V or O (OVerflow) - the result produced an overflow
• C (Carry) - the result produced a carry

'Negative' means that the result had the high bit set (i.e. when considered as a signed number, was negative). 'Carry' means that a carry occurred out of the top bit (e.g. a unsigned result that could not fit in the word length being used); 'Overflow' means that result, considered as a signed number, had a different sign from the operands (e.g. adding one to the largest possible positive number on a two's complement machine).

The concept was first used in the PDP-11. Some machines (e.g. the Motorola M68000 Family) use this scheme exactly; others (e.g. the Intel 8086 and descendants) add more condition code bits, e.g.:

• P - Parity
• A - Auxiliary carry

Some machines carry the condition codes in the Processor Status Word register, others (e.g. the Intel 8086) have a special 'Flags' register for them.

External links

• The PDP-11: A Case Study of How Not to Design Condition Codes