Difference between revisions of "OMNIBUS"
m (Typo) |
m (→External links: +OMNIBUS specification) |
||
| (8 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
| − | The '''OMNIBUS''' was [[Digital Equipment Corporation|DEC]]'s [[bus]] for the later [[PDP-8 family|PDP-8]]'s; it was introduced with the [[PDP-8/E]], in 1970. It provided three kinds of cycles (as in earlier PDP-8's): | + | The '''OMNIBUS''' was [[Digital Equipment Corporation|DEC]]'s [[peripheral]] [[bus]] for the later [[PDP-8 family|PDP-8]]'s; it was introduced with the [[PDP-8/E]], in 1970. It provided three kinds of cycles (as in earlier PDP-8's): |
| − | * ''Programmed data transfers'', in which the [[Central Processing Unit|CPU]] reads or writes data to the [[device controller]]; | + | * ''Programmed data transfers'', [[programmed I/O]], in which the [[Central Processing Unit|CPU]] reads or writes data to the [[device controller]]; |
| − | * ''Program interrupt transfers'' | + | * ''Program interrupt transfers'', in which the controller [[interrupt]]s the CPU; |
| − | * ''Data break transfers'', the PDP-8 term for [[Direct Memory Access|DMA]]. | + | * '''''Data break transfers''''', the PDP-8 term for [[Direct Memory Access|DMA]]. |
In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle. | In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle. | ||
| − | There were two different | + | There were two different forms of the data break. In the first, the [[three cycle data break]], the word count and buffer address are stored in main memory; an operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation (hence the name). In the second, the ''single cycle data break'', the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred; this had less bus overhead, but required a more complex controller. |
The OMNIBUS was physically implemented as a large [[backplane]], into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots. | The OMNIBUS was physically implemented as a large [[backplane]], into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots. | ||
In [[analog]] electrical terms, it was very similar to the [[UNIBUS]]; mostly bi-directional [[transmission line]]s, with a few uni-directional control lines. The [[terminator]]s and [[voltage]] levels of the two were the same, and they shared driver and receiver circuitry. | In [[analog]] electrical terms, it was very similar to the [[UNIBUS]]; mostly bi-directional [[transmission line]]s, with a few uni-directional control lines. The [[terminator]]s and [[voltage]] levels of the two were the same, and they shared driver and receiver circuitry. | ||
| + | |||
| + | {{semi-stub}} | ||
| + | |||
| + | ==See also== | ||
| + | |||
| + | *[[:Category: OMNIBUS Peripherals|OMNIBUS Peripherals]] | ||
| + | |||
| + | ==External links== | ||
| + | |||
| + | * [https://ethw.org/w/images/2/21/OMNI-spec.pdf OMNIBUS specification] | ||
| + | * [https://homepage.divms.uiowa.edu/~jones/pdp8/hard8e/modules.html OMNIBUS Modules] | ||
[[Category: DEC Buses]] | [[Category: DEC Buses]] | ||
| + | [[Category: OMNIBUS]] | ||
Latest revision as of 03:52, 19 September 2021
The OMNIBUS was DEC's peripheral bus for the later PDP-8's; it was introduced with the PDP-8/E, in 1970. It provided three kinds of cycles (as in earlier PDP-8's):
- Programmed data transfers, programmed I/O, in which the CPU reads or writes data to the device controller;
- Program interrupt transfers, in which the controller interrupts the CPU;
- Data break transfers, the PDP-8 term for DMA.
In addition to the usual read and write operations, a data break could also do an incremement operation, where a word was read out of main memory (core at the time), incremented, and written back during the 'write back' phase of the core cycle.
There were two different forms of the data break. In the first, the three cycle data break, the word count and buffer address are stored in main memory; an operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation (hence the name). In the second, the single cycle data break, the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred; this had less bus overhead, but required a more complex controller.
The OMNIBUS was physically implemented as a large backplane, into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots.
In analog electrical terms, it was very similar to the UNIBUS; mostly bi-directional transmission lines, with a few uni-directional control lines. The terminators and voltage levels of the two were the same, and they shared driver and receiver circuitry.
