Difference between revisions of "First-In First-Out buffer"
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FIFO buffers are found in both [[hardware]] and [[software]]; in the latter, they are usually implemented as [[ring buffer]]s, to avoid the un-productive overhead of shifting data around as data is added and removed. | FIFO buffers are found in both [[hardware]] and [[software]]; in the latter, they are usually implemented as [[ring buffer]]s, to avoid the un-productive overhead of shifting data around as data is added and removed. | ||
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| + | FIFO buffers are also used in [[serial line|serial communications]], where a [[UART]] needs to receive more data without [[interrupt]]ing the CPU. | ||
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| + | ==External links== | ||
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| + | * [https://www.tldp.org/HOWTO/Serial-HOWTO-18.html#ss18.3 Serial HOWTO: What Are UARTs? How Do They Affect Performance? - FIFOs] | ||
{{semi-stub}} | {{semi-stub}} | ||
[[Category:Hardware Basics]] | [[Category:Hardware Basics]] | ||
Latest revision as of 16:38, 10 April 2019
A First-In First-Out buffer (usually given as FIFO) is a form of buffer in which data is inserted at one end, and removed from the other, so that the data is retrieved in the same order as it went in - hence the name.
FIFO buffers are found in both hardware and software; in the latter, they are usually implemented as ring buffers, to avoid the un-productive overhead of shifting data around as data is added and removed.
FIFO buffers are also used in serial communications, where a UART needs to receive more data without interrupting the CPU.
