Difference between revisions of "Three cycle data break"
(copyedit, hdw savings details) |
m (Actually, now that I think about it, this one is probably better) |
||
| (One intermediate revision by the same user not shown) | |||
| Line 5: | Line 5: | ||
This moved some of the replicated [[logic]] needed to implement the I/O devices (such as the [[gate]]s needed to maintain the buffer information [[register]]s) from each I/O device into one shared set within the processor, thereby economizing on the hardware in the device. (Recall that this mechanism was used in an era when gates were constructed out of individual physical [[transistor]]s; [[integrated circuit]]s were still quite some distance into the future.) The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation). | This moved some of the replicated [[logic]] needed to implement the I/O devices (such as the [[gate]]s needed to maintain the buffer information [[register]]s) from each I/O device into one shared set within the processor, thereby economizing on the hardware in the device. (Recall that this mechanism was used in an era when gates were constructed out of individual physical [[transistor]]s; [[integrated circuit]]s were still quite some distance into the future.) The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation). | ||
| − | [[Category: DEC | + | [[Category: DEC Buses]] |
Latest revision as of 21:06, 15 June 2022
Three cycle data break was a form of DMA for high-speed peripherals (usually mass storage) to main memory, used on a number of early DEC computers.
The buffer address and word count were kept in main memory (at an address often specified by jumpers in the peripheral). This required the assistance of the processor to handle the operation, both placing it in charge of actually doing the transfer, and also maintaining the DMA address and word count. In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word.
This moved some of the replicated logic needed to implement the I/O devices (such as the gates needed to maintain the buffer information registers) from each I/O device into one shared set within the processor, thereby economizing on the hardware in the device. (Recall that this mechanism was used in an era when gates were constructed out of individual physical transistors; integrated circuits were still quite some distance into the future.) The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).
