Difference between revisions of "Condition codes"
m (typo) |
m (Typo) |
||
| Line 10: | Line 10: | ||
* C (Carry) - the result produced a carry | * C (Carry) - the result produced a carry | ||
| − | 'Negative' means that the result had the high bit set (i.e. when considered as a signed | + | 'Negative' means that the result had the high bit set (i.e. when considered as a signed number, was negative). 'Carry' means that a carry occurred out of the top bit (e.g. a unsigned result that could not fit in the word length being used); 'Overflow' means that result, considered as a signed number, had a different sign from the operands (e.g. adding one to the largest possible positive number on a two's complement machine). |
The concept was first used in the [[PDP-11]]. Some machines (e.g. the [[Motorola M68000 Family]]) use this scheme exactly; others (e.g. the [[Intel 8086]] and descendants) add more condition code bits, e.g.: | The concept was first used in the [[PDP-11]]. Some machines (e.g. the [[Motorola M68000 Family]]) use this scheme exactly; others (e.g. the [[Intel 8086]] and descendants) add more condition code bits, e.g.: | ||
| Line 19: | Line 19: | ||
Some machines carry the condition codes in the [[Processor Status Word]] [[register]], others (e.g. the Intel 8086) have a special 'Flags' register for them. | Some machines carry the condition codes in the [[Processor Status Word]] [[register]], others (e.g. the Intel 8086) have a special 'Flags' register for them. | ||
| − | + | ==Conditional branches== | |
By testing these bits, the complete complement of signed and unsigned conditional branches can be produced. E.g., on the PDP-11, | By testing these bits, the complete complement of signed and unsigned conditional branches can be produced. E.g., on the PDP-11, | ||
Revision as of 11:52, 21 October 2017
Condition codes are a way of recording high-level information about the results of arithmetic operations in a CPU, to allow later conditional branches to divert the control flow in the program, depending on the results of the arithmetic operation.
Combinations of various condition code bits can be interpreted for both two's complement signed computations as well as unsigned.
The basic set of condition code bits are:
- Z (Zero) - the result was 0
- N or S (Negative or Sign) - the result was negative
- V or O (OVerflow) - the result produced an overflow
- C (Carry) - the result produced a carry
'Negative' means that the result had the high bit set (i.e. when considered as a signed number, was negative). 'Carry' means that a carry occurred out of the top bit (e.g. a unsigned result that could not fit in the word length being used); 'Overflow' means that result, considered as a signed number, had a different sign from the operands (e.g. adding one to the largest possible positive number on a two's complement machine).
The concept was first used in the PDP-11. Some machines (e.g. the Motorola M68000 Family) use this scheme exactly; others (e.g. the Intel 8086 and descendants) add more condition code bits, e.g.:
- P - Parity
- A - Auxiliary carry
Some machines carry the condition codes in the Processor Status Word register, others (e.g. the Intel 8086) have a special 'Flags' register for them.
Conditional branches
By testing these bits, the complete complement of signed and unsigned conditional branches can be produced. E.g., on the PDP-11, this includes:
- BEQ - Zero, or equal (after comparing two quantities)
- BNE - Non-zero, or not equal
- BPL - Positive
- BMI - Negative
- BCS - Carry
- BCC - No Carry
- BVS - Overflow
- BVC - No Oveflow
Signed:
- BGE - Greater or Equal
- BGT - Greater
- BLE - Lesser or Equal
- BLT - Lesser
Unsigned:
- BLOS - Lower or the same
- BLO - Lower
- BHIS - Higher or the same
- BHI - Higher
