KEF11-B CIS chip: Difference between revisions
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[[Image:KEF11-B.jpg|250px|thumb|right|KEF11-B chip]] | |||
It consists of six [[integrated circuit|chips]] containing additional [[microcode]], on a large carrier. Due to its large size, not all the [[KDF11 CPUs]] can use it; the [[KDF11-A CPU]] is too small to hold | The '''KEF11-B CIS chip''' is an option for some [[PDP-11]] [[Central Processing Unit|CPU]] [[printed circuit board|boards]] which use the [[F-11 chip set]]; it implements the [[PDP-11 Commercial Instruction Set]]. | ||
It consists of six [[integrated circuit|chips]] containing additional [[microcode]], on a large dual carrier. Due to its large size, not all the [[KDF11 CPUs]] can use it and the [[KEF11-A floating point chip]] at the same time; the [[KDF11-A CPU]] is too small to hold them both simultaneously. | |||
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[[Category: PDP-11 Processors}} | |||
Revision as of 14:58, 1 November 2018
The KEF11-B CIS chip is an option for some PDP-11 CPU boards which use the F-11 chip set; it implements the PDP-11 Commercial Instruction Set.
It consists of six chips containing additional microcode, on a large dual carrier. Due to its large size, not all the KDF11 CPUs can use it and the KEF11-A floating point chip at the same time; the KDF11-A CPU is too small to hold them both simultaneously.
[[Category: PDP-11 Processors}}
