Difference between revisions of "PDP-10 memories"
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There were three generations of [[main memory]] systems for the [[PDP-10]]; the first two with the so-called external memory bus, in 18- and 22-bit [[address]] forms (for the [[KA10]]. and [[KI10]] and early [[KL10]], respectively), and the internal 'S-bus' (for the later KL10). (Memory for the [[KS10]], which was ''sui generis'', is not covered here.) | There were three generations of [[main memory]] systems for the [[PDP-10]]; the first two with the so-called external memory bus, in 18- and 22-bit [[address]] forms (for the [[KA10]]. and [[KI10]] and early [[KL10]], respectively), and the internal 'S-bus' (for the later KL10). (Memory for the [[KS10]], which was ''sui generis'', is not covered here.) | ||
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18-bit external: | 18-bit external: | ||
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* [[MB20 core memory|MB20]] | * [[MB20 core memory|MB20]] | ||
* [[MF20 MOS memory|MF20]] | * [[MF20 MOS memory|MF20]] | ||
| + | * [[MG20 MOS memory|MG20]] | ||
| − | The first two groups are all [[multi-port memory]] (generally 4 ports per memory system); the [[Central Processing Unit|CPU]] uses one port, the others are used by [[channel]]s for [[mass storage]] such as [[disk]]s. | + | The first two groups are all [[multi-port memory]] (generally 4 ports per memory system); the [[Central Processing Unit|CPU]] uses one port, the others are used by [[channel]]s for [[mass storage]] such as [[disk]]s. All except the MF20 and MG20 were [[core memory]], and almost all supported some level of [[interleaving]]. |
[[Category: PDP-10 memories]] | [[Category: PDP-10 memories]] | ||
Revision as of 02:21, 6 March 2019
There were three generations of main memory systems for the PDP-10; the first two with the so-called external memory bus, in 18- and 22-bit address forms (for the KA10. and KI10 and early KL10, respectively), and the internal 'S-bus' (for the later KL10). (Memory for the KS10, which was sui generis, is not covered here.)
18-bit external:
22-bit external:
Internal:
The first two groups are all multi-port memory (generally 4 ports per memory system); the CPU uses one port, the others are used by channels for mass storage such as disks. All except the MF20 and MG20 were core memory, and almost all supported some level of interleaving.
