Difference between revisions of "PDP-10 memories"
(S-Bus details) |
(all did parity, we think) |
||
| Line 27: | Line 27: | ||
* [[MG20 MOS memory|MG20]] | * [[MG20 MOS memory|MG20]] | ||
| − | The first two groups are all [[multi-port memory]] (generally 4 ports per memory system in the first group, and 8 in the second); the [[Central Processing Unit|CPU]] uses one port, the others are used by [[channel]]s for [[mass storage]] such as [[disk]]s. All except the MF20 and MG20 were [[core memory]], and | + | The first two groups are all [[multi-port memory]] (generally 4 ports per memory system in the first group, and 8 in the second); the [[Central Processing Unit|CPU]] uses one port, the others are used by [[channel]]s for [[mass storage]] such as [[disk]]s. All except the MF20 and MG20 were [[core memory]], and all supported [[parity]], and some level of [[interleaving]]. |
[[Category: PDP-10 memories]] | [[Category: PDP-10 memories]] | ||
Revision as of 19:45, 16 May 2020
There were three generations of main memory bus, and memory systems to attach to them, for the PDP-10 line; the first two with the so-called external memory bus, in 18- and 22-bit address forms (for the KA10. and KI10 and early KL10, respectively), and the last with the internal 'S-Bus' (for the later KL10). (Memory for the KS10, which was sui generis, is not covered here.)
There were minor differences between the two external bus types, requiring a KI10-M Memory Bus Adapter if 18-bit units are to be attached to a KI10. Similarly, 22-bit units can be attached to the S-Bus using a DMA20 Memory Bus Controller.
The S-Bus (and a later version, the X-Bus, used with MOS internal memory, such as the MF20) performs memory transfers in blocks of up to four words, so that four words can be read in any cycle; the block can start with any word within the block. The KL10 contains a pair of S-Busses, designated 0 and 1.
Memory systems
18-bit external:
22-bit external:
Internal:
The first two groups are all multi-port memory (generally 4 ports per memory system in the first group, and 8 in the second); the CPU uses one port, the others are used by channels for mass storage such as disks. All except the MF20 and MG20 were core memory, and all supported parity, and some level of interleaving.
