Difference between revisions of "MG20 MOS memory"
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<!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> | <!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> | ||
[[Error-correcting code|ECC]] is provided to protect the memory contents. The MG20 connected to the KL10's ugraded internal memory bus, the X-Bus. The MG20 was [[multi-port memory|single-port memory]], and could not be used in a [[multi-processor]] system, or with external [[channel]]s. | [[Error-correcting code|ECC]] is provided to protect the memory contents. The MG20 connected to the KL10's ugraded internal memory bus, the X-Bus. The MG20 was [[multi-port memory|single-port memory]], and could not be used in a [[multi-processor]] system, or with external [[channel]]s. | ||
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| + | ==See also== | ||
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| + | * [[MF20 MOS memory]] | ||
[[Category: PDP-10 memories]] | [[Category: PDP-10 memories]] | ||
Revision as of 16:45, 10 April 2021
The MG20 was a MOS DRAM main memory system for the later PDP-10s, principally the final KL10s (models KL10-E and KL10-R). An MG20 contained up to two storage groups, each with 1MW, for a maximum of 2MW; up to 2 MG20's could be connected to a single system, for a total of up to 4M.
The MG20 was basically an MF20 with 64Kx1 chips, instead of the 16Kx1 chips of the MF20. It appears that it was possible to upgrade an MF20 to an MG20 by replacing the four M8579 MOS Memory cards of each storage group of the MF20 with the M8570 MOS Memory cards of the MG20, and upgrading the power supply; the four control cards of the MF20:
- M8574 Write Path
- M8575 Syndrome
- M8576 Control and Timing
- M8577 Address and Timing
remained unchanged.
ECC is provided to protect the memory contents. The MG20 connected to the KL10's ugraded internal memory bus, the X-Bus. The MG20 was single-port memory, and could not be used in a multi-processor system, or with external channels.
